MAX7652CCB datasheet(27/36 Pages) MAXIM

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Flash Programmable 12-Bit Integrated

Data-Acquisition Systems

______________________________________________________________________________________

An external oscillator can also be used to clock the

MAX7651/MAX7652 at frequencies between 1 and

12MHz, provided that the duty cycle is between 40%

and 60%. When using an external clock source connect

the clock to XTAL1, with XTAL2 unconnected.

Applications Information

Performing a Conversion

An example of a conversion with the MAX7651/

MAX7652 is as follows:

• Write to the ADCON SFR, setting bit CCIE to 1, and

bits M3–M0 to appropriate values for the desired dif-

ferential or single-ended analog input configuration

(Tables 6 and 7).

• Wait 224 clock cycles to receive Interrupt 3 as an

indication that the A/D conversion is complete.

• Read the conversion data in SFRs ADDAT0 and

ADDAT1 as described in Tables 8 and 9.

Using FLASH Memory

The upper and lower 8kB blocks of internal Flash mem-

ory are each organized as 128 64-byte pages. Read,

write, and page-erase operations cannot be applied to

either block while executing program commands from

the other block.

Note: Standard MOVC operations are supported.

FLASH Memory Special Function Registers

Tables 17 and 18 show the formats for the EEAH and

EEAL SFRs. The EEAH register specifies the applicable

Flash memory block (high or low) and the page address

within that block. The EEAL register specifies the byte

address within the specified page.

Table 19 shows the format for the Flash memory data

(EEDAT) SFR that is used for 8-bit read and write trans-

fers from and to a specified address.

Table 20 shows the format for the Flash memory status

and command (EESTCMD) SFR. Bits RDYHI and

RDYLO are cleared to zero when a read, write, or page-

erase operation is applied to the high or low flash mem-

ory block. These bits are set to one once the flash

NAME

SFR

BIT

DESCRIPTION

WDIF

EICON

Watchdog Interrupt Flag. WDIF is set to 1 after completion of the interrupt timeout period (see

Table 14). WDIF must be cleared by software before exiting interrupt service routine. Otherwise

interrupt reoccurs upon exiting. WDIF is automatically cleared by either an external RST

assertion or a WDT-generated reset.

WTRF

WDT

Watchdog Reset Flag. The WTRF bit is a status/control bit indicating that the Watchdog counter

has counted an additional 512 clocks past the WDT interrupt and has generated a processor

RESET. The 8051’s “reset” routine should check the WTRF flag to determine the source of the

reset. Additionally, if the WTRF flag has been set the Watchdog Timer counts will be reset when

a zero is written to the WTRF flag. This allows the processor to regain synchronization with the

WDT after a WDT reset has occurred. WTRF is also cleared when a zero is written to it.

EWT

EICON

Enable Watchdog Timer. Set to 1 to enable the watchdog timer. An assertion at the external

RST pin automatically clears EWT. If EWT is cleared after being set. The watchdog timer count

will suspend until EWT is set to 1 again.

RWT

EICON

Reset Watchdog Timer. Writing a “1" to the RWT bit will reset the watchdog counter ONLY if the

end of the count has been reached (WDIF = 1) and the 512 clock window has not expired

(WTRF = 0). Writing to RWT before the timeout period will not reset the watchdog timer.

WD1

CKCON

Watchdog Control Bit 1. Controls the watchdog interrupt timeout (see Table 14).

WD0

CKCON

Watchdog Control Bit 0. Controls the watchdog interrupt timeout (see Table 14).

EWDI

EIE

Enable Watchdog Interrupt. An interrupt will be generated after the interrupt timeout period

when EWDI = 1. Either a WDT-generated reset or an assertion at the external RST pin

automatically clears EWDI.

Table 17. Watchdog Timer Control and Status Bits

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