Flash Programmable 12-Bit Integrated

Data-Acquisition Systems

16

______________________________________________________________________________________

Pin Description (continued)

PIN

NAME

FUNCTION

P0.5: Bit 5 for General Purpose I/O Port 0

46

P0.5/

AD5

AD5: Bit 5 for Internal Flash Memory Data or external memory I/O

P0.6: Bit 6 for General Purpose I/O Port 0

47

P0.6/

AD6

AD6: Bit 6 for Internal Flash Memory Data or external memory I/O

P0.7: Bit 7 for General Purpose I/O Port 0 (most significant bit)

48

P0.7/

AD7

AD7: Bit 7 for Internal Flash Memory Data or external memory I/O

P1.0: Bit 0 for General Purpose I/O Port 1 (least significant bit)

T2: Timer 2 External Input

T2OUT: Timer 2 External Output

49

P1.0/T2/

T2OUT/

AD0

AD0: Bit 0 for Internal Flash Memory Address

P1.1: Bit 1 for General Purpose I/O Port 1

T2EX: Timer 2 External Capture/Reload Trigger

50

P1.1/

T2EX/

AD1

AD1: Bit 1 for Internal Flash Memory Address

P1.2: Bit 2 for General Purpose I/O Port 1

RXD1: Receive Serial Input for UART 1

51

P1.2/

RXD1/

AD2

AD2: Bit 2 for Internal Flash memory Address

P1.3: Bit 3 for General Purpose I/O Port 1

TXD1: Transmit Serial Input for UART 1

52

P1.3/

TXD1/

AD3

AD3: Bit 3 for Internal Flash Memory Address

P1.4: Bit 4 for General Purpose I/O Port 1

53

P1.4/

AD4

AD4: Bit 4 for Internal Flash Memory Address

P1.5: Bit 5 for General Purpose I/O Port 1

54

P1.5/

AD5

AD5: Bit 5 for Internal Flash Memory Address

P1.6: Bit 6 for General Purpose I/O Port 1

55

P1.6/

AD6

AD6: Bit 6 for Internal Flash Memory Address

P1.7: Bit 7 for General Purpose I/O Port 1

56

P1.7/

AD7

AD7: Bit 7 for Internal Flash Memory Address

57

58

RST

Active High Reset. Connected to an internal 130k

Ω pulldown resistor. Connect a 2.2µF (typ) capacitor from

59

XTAL2

Clock Output. Connect a crystal across XTAL1 and XTAL2. The on-chip clock signal is not available at

XTAL2. Leave XTAL2 unconnected when XTAL1 is driven with an external clock.

60

XTAL1

Clock Input. Connect a crystal across XTAL1 and XTAL2. Alternatively, drive XTAL1 with a CMOS-

compatible clock and leave XTAL2 unconnected.

61

DGND

Digital Ground. Connect pins 27, 39, and 61 together.

62

Positive Digital Supply Voltage. Bypass with a 0.1µF in parallel with a 10µF low ESR capacitor to DGND.

Connect pins 28, 40 and 62 together.

63

TEST

Test Point. Must be connected to DGND.

64

ACOM

Analog Common Input. Negative differential input relative to AIN_ for single-ended