10-Bit Low Power 2-Wire Interface Serial,

Voltage-Output DAC

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7

Detailed Description

The MAX5811 is a 10-bit, voltage-output DAC with an

consists of a serial interface, power-down circuitry,

input and DAC registers, a 10-bit resistor string DAC,

unity-gain output buffer, and output resistor network.

The serial interface decodes the address and control

bits, routing the data to either the input or DAC register.

Data can be directly written to the DAC register imme-

diately updating the device output, or can be written to

the input register without changing the DAC output.

Both registers retain data as long as the device is pow-

ered.

DAC Operation

The MAX5811 uses a segmented resistor string DAC

architecture, which saves power in the overall system

and guarantees output monotonicity. The MAX5811’s

input coding is straight binary, with the output voltage

given by the following equation:

where N = 10 (bits), and D = the decimal value of the

input code (0 to 1023).

Output Buffer

The MAX5811 analog output is buffered by a precision,

unity-gain follower that slews at about 0.5V/µs. The

buffer output swings rail-to-rail, and is capable of dri-

ving 5k

Ω in parallel with 200pF. The output settles to

±0.5LSB within 4µs.

Power-On Reset

The MAX5811 features an internal POR circuit that ini-

tializes the device upon power-up. The DAC registers

are set to zero scale and the device is powered-down

with the output buffer disabled and the output pulled to

GND through the 100k

Ω termination resistor. Following

power-up, a wake-up command must be initiated

before any conversions are performed.

Power-Down Modes

The MAX5811 has three software-controlled low-power

power-down modes. All three modes disable the output

reducing supply current draw to 300nA. In power-down

mode 0, the device output is high impedance. In

power-down mode 1, the device output is internally

pulled to GND by a 1k

Ω termination resistor. In power-

down mode 2, the device output is internally pulled to

GND by a 100k

Ω termination resistor. Table 1 shows

the power-down mode command words.

Upon wake-up, the DAC output is restored to its previ-

ous value. Data is retained in the input and DAC regis-

ters during power-down mode.

Digital Interface

wire interface consisting of a serial data line (SDA) and

V

VD

OUT

REF

N

=

2

Pin Description

PIN

NAME

FUNCTION

Power Supply and DAC Reference Input

2

GND

Ground

3

SDA

Bidirectional Serial Data I/O

4

SCL

Serial Clock Line

5

ADD

Address Select. A logic high sets the address LSB to 1, a logic low sets the address LSB to 0.

6

OUT

Analog Output

Table 1. Power-Down Command Bits

POWER-DOWN

COMMAND BITS

PD1

PD0

MODE/FUNCTION

0

0

Power-up device. DAC output restored to previous value.

0

1

Power-down mode 0. Power-down device with output floating.

1

0

Power-down mode 1. Power-down device with output terminated with 1k

Ω to GND.

1

1

Power-down mode 2. Power-down device with output terminated with 100k

Ω to GND.