MAX5811 datasheet(3/13 Pages) MAXIM

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10-Bit Low Power 2-Wire Interface Serial,

Voltage-Output DAC

_______________________________________________________________________________________

Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by design for TA = TMIN to TMAX.

Note 2: Static specifications are tested with the output unloaded.

Note 3: Linearity is guaranteed from codes 29 to 995.

Note 4: Offset and gain error limit the FSR.

Note 5: Guaranteed by design. Not production tested.

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +2.7V to +5.5V, GND = 0, RL = 5k

Ω, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at

VDD = +5V, TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DYNAMIC PERFORMANCE

Voltage-Output Slew Rate

0.5

V/µs

Voltage-Output Settling Time

To 1/2LSB code 100 hex to 300 hex or 300

hex to 100 hex (Note 5)

412

µs

Digital Feedthrough

Code = 000 hex, digital inputs from 0 to VDD

0.2

nV-s

Digital-to-Analog Glitch Impulse

Major-carry transition (code = 1FF hex to 200

hex and 200 hex to 1FF hex)

nV-s

POWER SUPPLIES

Supply Voltage Range

VDD

2.7

5.5

All digital inputs at 0 or VDD = 3.6V

100

170

Supply Current with

No Load

All digital inputs at 0 or VDD = 5.5V

130

190

Power-Down Supply Current

All digital inputs at 0 or VDD = 5.5V

0.3

µA

TIMING CHARACTERISTICS (Figure 1)

Serial Clock Frequency

fSCL

400

kHz

Bus-Free Time Between STOP

and START Conditions

tBUF

1.3

µs

START Condition Hold Time

tHD,STA

0.6

µs

SCL Pulse Width Low

tLOW

1.3

µs

SCL Pulse Width High

tHIGH

0.6

µs

Repeated START Setup Time

tSU,STA

0.6

µs

Data Hold Time

tHD,DAT

0.9

µs

Data Setup Time

tSU,DAT

100

SDA and SCL Receiving

Rise Time

(Note 5)

300

SDA and SCL Receiving

Fall Time

(Note 5)

300

SDA Transmitting Fall Time

(Note 5)

20 +

0.1Cb

250

STOP Condition Setup Time

tSU,STO

0.6

µs

Bus Capacitance

(Note 5)

400

Maximum Duration of

Suppressed Pulse Widths

tSP

050

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