Low-Cost, Voltage-Output, 16-Bit DACs with

Internal Reference in µMAX

10

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Applications Information

Power-Supply and Bypassing

Considerations

Bypass the power supply with a 10µF capacitor in par-

allel with a 0.1µF capacitor to AGND. Minimize lead

lengths to reduce lead inductance. If noise becomes

an issue, use shielding and/or ferrite beads to increase

isolation.

Output Buffer

The MAX5200–MAX5203 include low-offset, low-noise

buffers enabling the output to source 15mA or sink

5mA. The output buffer operates at a slew rate of

0.6V/µs. With a 1/4 FS to 3/4 FS output transition, the

buffer output typically settles to 1 LSB in less than

25µs. The MAX5200–MAX5203 output buffers provide a

low 0.2

Ω typical output impedance. The MAX5200–

MAX5203 buffer amplifiers typically produce

175nV/

√Hz noise at 10kHz.

SHUTDOWN

WAKE-UP

SHUTDOWN

WAKE-UP

SCLK

CS

A. WAKING UP USING A THIRD FALLING EDGE ON CS.

B. WAKING UP USING A TRANSITION ON SCLK.

SCLK

CS

Figure 4. Shutdown Timing

D14

D15

D0

SCLK

CS

DIN

LDAC

Figure 3. 4-Wire Interface Timing Diagram