Low-Cost, Voltage-Output, 16-Bit DACs with

Internal Reference in µMAX

8

_______________________________________________________________________________________

Detailed Description

The MAX5200–MAX5203 serial 16-bit, voltage-output

DACs are easily configured with a 3-wire serial inter-

face. These devices offer full 16-bit performance with

less than ±20LSB integral linearity error and less than

±1LSB differential linearity error, thus ensuring monoto-

nic performance. Serial data transfer minimizes the

number of package pins required. The MAX5200–

MAX5203 include control-logic circuitry, a 16-bit data-in

shift register, and a DAC register. In addition, these

devices employ a precision-bandgap reference and

trimmed internal resistors to produce a gain of 2V/V,

maximizing

the

output

voltage

swing.

The

MAX5200–MAX5203 output is buffered and the full-

The MAX5200–MAX5203 feature a hardware reset input

(CLR) that, when pulled low, clears the DAC output to

zero code 0000H (MAX5201/MAX5203) or resets the

DAC output to midscale code 8000 hex (MAX5200/

Internal Reference

The MAX5200/MAX5201 (+5V supply) include an inter-

nal reference of 2.5V while the MAX5202/MAX5203

(+3V supply) include an internal reference of 1.5V. The

external circuitry from this reference. To improve DAC

output noise performance, bypass with a low leakage

0.1µF minimum capacitor to AGND.

Digital Interface

The MAX5200–MAX5203 digital interface is a standard

3-wire connection compatible with SPI/QSPI/

MICROWIRE and most DSP interfaces. All of the digital

input pins (CS, SCLK, DIN, CLR, and LDAC) are TTL

compatible. SCLK can accept clock frequencies as

high as 10MHz for a +5V supply and 10MHz for a +3V

or +3.3V supply.

One of two methods can be used when interfacing and

updating the MAX5200–MAX5203. The first requires

three digital inputs: CS, DIN, and SCLK (Figure 2). The

active-low chip-select input (CS) enables the serial

Pin Description

PIN

NAME

FUNCTION

1

CLR

Reset DAC Active-Low Input. Pull

CLR low to reset the DAC output to midscale output (8000 hex) for

MAX5200/MAX5202 and to zero-scale output (0000 hex) for MAX5201/MAX5203. For normal

operation, connect

2

REF

Reference Voltage Output. Provides a +2.5V (MAX5200/MAX5201) or +1.5V (MAX5202/MAX5203)

nominal output. For improved noise performance, bypass with a minimum 0.1µF capacitor to AGND.

3

AGND

Analog Ground

capacitor.

5

OUT

DAC Output Voltage

6

CS

Active-Low Chip-Select Input

7

LDAC

Load DAC Input

8DIN

Serial Data Input

9

SCLK

Serial Clock Input. Duty cycle must be 40% to 60%.

10

DGND

Digital Ground

CLR

AGND

REF

16-BIT DAC

BANDGAP

REF

16-BIT DATA LATCH

DIN

SCLK

CS

CONTROL

LOGIC

LDAC

OUT

DGND

MAX5200–

MAX5203

SERIAL INPUT REGISTER

Figure 1. MAX5200–MAX5203 Simplified Functional Diagram