Dual-Phase, Parallelable, Average-Current-Mode

Controllers

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13

The MAX5038A/MAX5041A accept an input voltage

range of +4.75V to +5.5V or +8V to +28V. All internal

control circuitry operates from an internally regulated

SGND with 4.7µF and 0.1µF low-ESR ceramic capacitors

in parallel for high-frequency noise rejection and stable

operation (Figures 1 and 2).

Calculate power dissipation in the MAX5038A/

MAX5041A as a product of the input voltage and the

charge of the low-side and high-side external

quency of each individual phase.

For applications utilizing a +5V input voltage, disable

Undervoltage Lockout (UVLO)/Soft-Start

The MAX5038A/MAX5041A include an undervoltage

lockout with hysteresis and a power-on reset circuit for

converter turn-on and monotonic rise of the output volt-

age. The UVLO threshold is internally set between

+4.0V and +4.5V with a 200mV hysteresis. Hysteresis

at UVLO eliminates “chattering” during startup.

Most of the internal circuitry, including the oscillator,

turns on when the input voltage reaches +4V. The

MAX5038A/MAX5041A draw up to 4mA of current before

the input voltage reaches the UVLO threshold.

The compensation network at the current-error ampli-

fiers (CLP1 and CLP2) provides an inherent soft-start of

the output voltage. It includes a parallel combination of

capacitors (C28, C30) and resistors (R5, R6) in series

with other capacitors (C27, C29) (see Figures 1 and 2).

The voltage at CLP_ limits the maximum current avail-

able to charge output capacitors. The capacitor on

CLP_ in conjunction with the finite output-drive current

of the current-error amplifier yields a finite rise time for

the output current and thus the output voltage.

Internal Oscillator

The internal oscillator generates the 180° out-of-phase

clock signals required by the pulse-width modulation

voltage ramp signals necessary for the PWM compara-

tors. Connect CLKIN to SGND to set the internal oscillator

internal oscillator to 500kHz.

CLKIN is a CMOS logic clock input for the phase-

locked loop (PLL). When driven externally, the internal

oscillator locks to the signal at CLKIN. A rising edge at

CLKIN starts the ON cycle of the PWM. Ensure that the

external clock pulse width is at least 200ns. CLKOUT

provides a phase-shifted output with respect to the ris-

ing edge of the signal at CLKIN. PHASE sets the

amount of phase shift at CLKOUT. Connect PHASE to

for 90° of phase shift, or connect PHASE to SGND for

60° of phase shift with respect to CLKIN.

The MAX5038A/MAX5041A require compensation on

PLLCMP even when operating from the internal oscillator.

The device requires an active PLL in order to generate

the proper clock signal required for PWM operation.

Control Loop

The MAX5038A/MAX5041A use an average-current-

mode control scheme to regulate the output voltage

(Figures 3a and 3b). The main control loop consists of

an inner current loop and an outer voltage loop. The

age. The inner current loop absorbs the inductor pole

reducing the order of the outer voltage loop to that of a

single-pole system.

The current loop consists of a current-sense resistor

amplifier (CEA_), an oscillator providing the carrier

ramp, and a PWM comparator (CPWM_). The precision

of 18. The inverting input to the CEA_ senses the CA_

output. The CEA_ output is the difference between the

voltage-error amplifier output (EAOUT) and the ampli-

fied voltage from the CA_. The RC compensation net-

work connected to CLP1 and CLP2 provides external

frequency compensation for the respective CEA_. The

start of every clock cycle enables the high-side drivers

and initiates a PWM ON cycle. Comparator CPWM_

compares the output voltage from the CEA_ with a 0 to

+2V ramp from the oscillator. The PWM ON cycle termi-

nates when the ramp voltage exceeds the error voltage.

(1)

(2)