SM34 Data Sheet #:

TM095

Page 25

Rev:

05 Date: 11/19/12

© Copyright 2012 The Connor-Winfield Corp. All Rights Reserved

Specifications subject to change without notice

Master / Slave Configuration

Figure 8

STC3500

SM34

8 kHz

M/S REF

REF 8

REF 1

#2

SM34

#1

M/S REF

8 kHz

Synchronized clock output

Synchronized clock output

REF1

REF8

REF1

REF8

8K_OUT

OUTPUT1

BITS_CLK

OUTPUT1

8K_OUT

BITS_CLK

BITS c lock output

BITS clock output

Application Notes

Acceptable output frequencies are: 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz or 77.76MHz. The device will

autodetect the output frequency.

Reference Inputs – The application may supply up to 8 reference inputs, applied at input pins Ref1 - 8. They may each be 8

kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz or 77.76 MHz. The device auto-detects the

reference frequencies, and they may be read from the Ref(1-8)_Frq_Priority registers in register control mode, as described in the

control mode sections that follow.

Reference switches are performed in a hitless manner. However, if the application externally changes the frequency of a particular

reference, the device requires 20ms to auto-detect the new frequency. Manual switches to a frequency changed reference should not

be made during this interval. Automatic reference selection mode accounts for the auto-detection in the reference qualification.

References would typically (but need not be) connected in decreasing order of usage priority. For example if redundant BITS clocks

are available, they would typically be assigned to

Ref1 and Ref2, with other transmission derived signals following thereafter.

Master/Slave operation – For some applications, reliability requirements may demand that the clock system be duplicated. The

SM34 device will support the master/slave duplicated configuration for such applications. To facilitate it’s use, the device includes the

necessary signal cross coupling and control functions. Redundancy for reliability implies two major considerations: 1) Maintaining

separate failure groups such that a failure in one group does not affect it’s mate, and 2) Physical and logical partitioning for repair,

such that a failed component can be replaced while the mate remains in service, if so desired. System design needs to account to

meet system level goals.