SM34 Data Sheet #:

TM095

Page 17

Rev:

05 Date: 11/19/12

© Copyright 2012 The Connor-Winfield Corp. All Rights Reserved

Specifications subject to change without notice

Register Descriptions and Operation continued

Intr_Event, 0x12 (R)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Lossof

Lossof

Activerefer-

DPLLMode

M/SRef

M/SRef

Anyrefer-

Anyrefer-

Lock

Signal

encechange

status

Changefrom

Changefrom erencechange erencechange

change

noactivityto

activitytono

fromnot

fromavailable

noactivity

activity

availableto

abletonot

available

available

Interruptstate=1.Whenanenabledinterruptoccurs,theSPI_INTpinisasserted,activelow.Allinterruptsarecleared

andtheSPI_INTpinpulledhighwhentheregisterisread.Resetdefaultis0.SeeDetailedDescriptionsectionunder

InterruptsandReferenceChangeinAutonomousModeandInterruptsinManualMode

Intr_Enable, 0x13 (R/W)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EnableInter- EnableInter-

EnableInter- EnableInter- EnableInter-

EnableInter-

EnableInter-

EnableInter-

ruptevent7: ruptevent6:

ruptevent5: ruptevent4: ruptevent3:

ruptevent2:

ruptevent1:

ruptevent0:

1:Enable

1:Enable

1:Enable

1:Enable

1:Enable

1:Enable

1:Enable

1:Enable

0:Disable

0:Disable

0:Disable

0:Disable

0:Disable

0:Disable

0:Disable

0:Disable

Default:0

Default:0

Default:0

Default:0

Default:0

Default:0

Default:0

Default:0

EnablesordisablesthecorrespondinginterruptsfromassertingtheSPI_INTpin.Interrupteventsstillappearinthe

Intr_Eventregisterindependentoftheir“enable”state.Resetdefaultisinterruptsdisabled.

Ref(1-8)_Frq_Offset, 0x14 ~ 0x1b (R)

Bit 7 ~ Bit 0

2’scomplementvalueoffrequencyoffsetbetweenreferenceandcalibratedlocaloscillator,0.2ppmresolution

Theseregistersindicatethefrequencyoffset,in0.2ppmresolution,betweeneachreferenceandthelocalcalibrated

oscillator.0x14-0x1bcorrespondtoRef1-Ref8.

Ref(1-8)_Frq_Priority, 0x1c ~ 0x23 (R/W)

Bit 7 ~ Bit 4

Bit 3

Bit 2 ~ Bit 0

Frequency

Revertivity

Priority

0000:None

1:revertive

000:Highest

0001:8kHz

0:non-revertive

111:Lowest

0010:1.544MHz

Default:0,

Default:0

0011:2.048MHz

nonrevertive

0100:12.96MHz

0101:19.44MHz

0110:25.92MHz

0111:38.88MHz

1000:51.84MHz

1001:77.76MHz

1010-1111:Reserved

BITS2-0indicatethepriorityofeachreferenceforuseinautomaticreferenceselectionmode(bit1oftheCtl_Mode

register=0).Inmanualreferenceselectionmode(bit1oftheCtl_Moderegister=1),theseBITSareread-onlyandwill

containeithertheresetdefaultorvalueswrittenwhenlastinautomaticreferenceselectionmode.Forequalpriority

values,lowerreferencenumbershavehigherpriority.

Bit3specifiesifthereferenceisrevertiveornon-revertiveinautomaticreferenceselectionmode.Whenareference

fails,thenexthighestpriority“available”(signalpresent,non-masked,andacceptablefrequencyoffset)referencewill

beselected.Whenareferencereturns,itwillbeswitchedtoonlyifitisofhigherpriorityandthecurrentactivereference

ismarked“Revertive”.

BITS7-4indicatetheauto-detectedfrequencyforeachreference.Invalidfrequenciesmayresultinerroneous

deviceoperation.Ifthereisnoactivityonareference,bits7-4willbe=0000.Bits7-4arereadonly.0x1c-0x23

correspondtoRef1-Ref8.