+3.0V to +5.5V, 1.25Gbps/2.5Gbps

Limiting Amplifiers

12

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The buffer’s output impedance is determined by the par-

allel combination of internal and external pullup resistors,

which are chosen to match the impedance of the trans-

mission line (Figure 1). The output buffer can be AC- or

DC-coupled to the load.

PECL Output Buffer

The MAX3268/MAX3269/MAX3768 offer an industry-

standard PECL output. The PECL outputs should be

put circuit. The squelch function forces OUT+ to a high

level and OUT- to a low level when the input is below

the programmed LOS threshold. In the 10-pin µMAX,

SQUELCH is left unconnected.

__________________Design Procedure

Program the LOS Assert Threshold

The loss-of-signal threshold is programmed by external

the Typical Operating Characteristics.

Select the Coupling Capacitors

ed to minimize the receiver’s deterministic jitter. Jitter is

placed at a low frequency:

π(50)(C)]

For Fibre Channel, Gigabit Ethernet, or other applica-

≥

or other applications using scrambled NRZ data, select

Select the Offset-Correction Capacitor

(MAX3264/MAX3265 TSSOP Only)

To maintain stability, it is important to keep a one-

cuit.

For Fibre Channel, Gigabit Ethernet, or other applica-

tions using 8B/10B data coding, leave pins CAZ1, and

≥

GND

ESD

STRUCTURES

OUT-

OUT+

Figure 6. PECL Output Circuit

GND

LEVEL

ESD

STRUCTURES

100

Ω

100

Ω

OUT-

OUT+

Figure 7. CML Output Circuit