+3.0V to +5.5V, 1.25Gbps/2.5Gbps

Limiting Amplifiers

10

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_______________Detailed Description

Figure 3 is a functional diagram of the MAX3264/

MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 lim-

iting amplifiers. A linear input buffer drives a multistage

limiting amplifier and an RMS power-detection circuit.

Offset correction with lowpass filtering ensures low

deterministic jitter. The output buffer produces a limited

output signal. The MAX3264/MAX3265/MAX3765 pro-

duce a CML output, while the MAX3268/MAX3269/

MAX3768 produce a PECL-compatible output signal.

Schematics of these input/output circuits are shown in

Figures 4 through 7.

RMS Power Detect with

Loss-of-Signal Indicator

An RMS power detector looks at the signal from the

input buffer and compares it to a threshold set by the

TH resistor (see Typical Operating Characteristics for

appropriate resistor values). The signal-detect informa-

tion is provided to the LOS outputs, which are internally

terminated with 8k

Ω (MAX3265/MAX3269/MAX3765) or

16k

Ω (MAX3264/MAX3268/MAX3768) pullup resistors.

The LOS outputs meet TTL voltage specifications when

loaded with a resistor

≥ 4.7kΩ.

CONTROL

GAIN

TH

Ω (MAX3265/MAX3269/MAX3765)

Ω (MAX3264/MAX3268/MAX3768)

LOS

LOS

OUT+

OUT-

SQUELCH

LEVEL

INPUT

BUFFER

CAZ1

CAZ2

OFFSET

CORRECTION

100

Ω

IN+

IN-

MAX3264

MAX3265

MAX3268

MAX3269

MAX3765

MAX3768

LOW-

PASS

100pF

TOTAL GAIN = 55dB (MAX3264/MAX3268/MAX3768)

TOTAL GAIN = 49dB (MAX3265/MAX3269/MAX3765)

POWER DETECT

WITH

COMPARATOR

OUTPUT

BUFFER

TTL

TTL

Figure 3. Functional Diagram