DBS Direct Downconverter

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7

Pin Description (continued)

NAME

FUNCTION

PIN

34

MOD-

PECL Modulus Control. A PECL low on MOD- sets the dual-modulus prescaler to divide by 32. A

PECL logic high sets the divide ratio to 33. Drive with a differential PECL signal in conjunction with

MOD+ (pin 33).

35

PLLIN+

PECL Phase-Locked Loop Input. Drive with a differential PECL signal in conjunction with PLLIN- (pin 36).

37

LOBUF+/

PSOUT+

LOBUFSEL = GND: PECL Prescaler Output. Differential output of the dual-modulus prescaler. Used in

Ω LO buffer

noninverting output.

36

PLLIN-

PECL Phase-Locked Loop Input. Drive with a differential PECL signal in conjunction with PLLIN+ (pin 35)

42

TANK-

LO Tank Oscillator Input. Connect to an external LC tank with varactor tuning.

38

LOBUF-/

PSOUT-

LOBUFSEL = GND: PECL Prescaler Output. Differential output of the dual-modulus prescaler. Used in

conjunction with PSOUT+. Requires PECL-compatible termination.

Ω LO buffer inverting output.

43

VRLO

LO Internal Regulator. Bypass with a 1000pF ceramic chip capacitor to GND.

44

TANK+

LO Tank Oscillator Input. Connect to an external LC tank with varactor tuning.

47

FB

Feedback Input for Loop Filter

48

CP

Voltage Drive Output. Control of external charge-pump transistor.

50%

MOD+,

MOD-

PSOUT+

PSOUT-

50%

50%

50%

Figure 1. Modulus Control Timing Diagram