DBS Direct Downconverter

6

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NAME

FUNCTION

PIN

Pin Description

2

CFLT

External Bypass for Internal Bias. Bypass this pin with a 0.1

µF ceramic chip capacitor to GND.

3

XTL-

Inverting Input to Crystal Oscillator. Consult crystal manufacturer for circuit loading requirements.

4

XTL+

Noninverting Input to Crystal Oscillator. Consult crystal manufacturer for circuit loading requirements.

5, 9, 10, 16,

40, 41, 46

GND

Ground. Connect each of these pins to a solid ground plane. Use multiple vias to reduce inductance

where possible.

7

RFIN-

RF Inverting Input. Bypass RFIN- with 47pF capacitor in series with a 75

Ω resistor to GND.

8

RFIN+

RF Noninverting Input. Connect to 75

Ω source with a 47pF ceramic chip capacitor.

11

QDC-

Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from QDC- to QDC+ (pin 12).

12

QDC+

Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from QDC+ to QDC- (pin 11).

13

IDC-

Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from IDC- to IDC+ (pin 14).

14

IDC+

Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from IDC+ to IDC- (pin 13).

17

RFOUT

Buffered RF Output. Enabled when INSEL is low.

18

CPG1

Charge-Pump Gain Select. High-impedance digital input. Sets the charge-pump output scaling. See

DC Electrical Characteristics for available gain settings.

20

XTLOUT

Buffered Crystal Oscillator Output

21

CPG2

Charge-Pump Gain Select. High-impedance digital input. Sets the charge-pump output scaling. See

DC Electrical Characteristics for available gain settings.

22

GC1

Gain Control Input for RF Front End. High-impedance analog input, with an input range of +1V to +4V.

See AC Electrical Characteristics for transfer function.

23

GC2

Gain Control Input for Baseband Signals. High-impedance analog input, with an input range of +1V to

+4V. See AC Electrical Characteristics for transfer function.

24

INSEL

Loopthrough Mode Enable. High-impedance digital input. Drive low to enable the RFOUT buffer and

disable the LO converters. Drive high for normal tuner operation.

25

FLCLK

Baseband Filter Cutoff Adjust. Connect to a slew-rate-limited clock source. See AC Electrical

Characteristics for transfer function.

26

RFBAND

RF Input Band Select Input. Drive high to enable 1680 MHz to 2175 MHz band. Leave unconnected to

enable 1180 MHz to 1680 MHz band. Connect to GND to enable 925 MHz to 1180 MHz band.

27

QOUT-

Baseband Quadrature Output. Connect to inverting input of high-speed ADC.

28

QOUT+

Baseband Quadrature Output. Connect to noninverting input of high-speed ADC.

30

IOUT-

Baseband In-Phase Output. Connect to inverting input of high-speed ADC.

31

IOUT+

Baseband In-Phase Output. Connect to noninverting input of high-speed ADC.

32

LODIVSEL

LO Buffer Divider Ratio Input. Drive high to enable divide-by-one LO buffer output. Connect to GND to

enable divide-by-two buffer output.

1, 6, 19,

29, 39, 45

the nearest GND with a ceramic chip capacitor.

15

LOBUFSEL

DIV1 to select DIV2 LO buffer output.

33

MOD+

PECL Modulus Control. A PECL high on MOD+ sets the dual-modulus prescaler to divide by 32. A PECL

logic low sets the divide ratio to 33. Drive with a differential PECL signal in conjunction with MOD- (pin 34).