LTC2000_15 datasheet(39/52 Pages) LINER

39 / 52 page

LTC2000

2000f

For more information www.linear.com/LTC2000

applications inFormation

procedure as when operating in dual port mode—DAC

sample clocks must all be aligned to arrive at the CKP/N

pins of all DACs simultaneously and timing mismatch

between LVDS data clock signals at the DCKIP/N pins of

all DACs must be less than 0.4 cycles of the DAC sample

clock, minus any timing mismatch between the DAC

sample clocks.

TodeterminewhetheranyDACsarebeingupdatedonecycle

late in single port mode, first use the phase comparator

outputs SYNC_PH and Table 13 to determine the delay

from the DCKIP/N rising edge to the next CKP/N falling

edge (as opposed to rising edge in dual port mode) for

each DAC. If the difference between the delays indicated

by SYNC_PH is greater than 0.4 cycles, the DCKIP/N ris-

ing edges are arriving in different sample clock cycles.

For the example in Figure 15b, we might read 0x15 for

SYNC_PH on DAC X and 0x20 on DAC Y. Table 13 shows

that the DCKIP/N to CKP/N delay is greater than 0.8 cycles

for DAC X and less than 0.1 cycles for DAC Y, and thus the

differencebetweenthemisatleast0.7cycles.Thisindicates

that DAC X is being updated one cycle later than DAC Y.

Consult Table 13 and use the same procedure described

above in the dual-port mode case to correct the SYNC_PS

settings for those DACs that are updating one cycle late.

In this single port example, writing 0x06 to register 0x05

of DAC X would set SYNC_MSYN = 1 and SYNC_PS = 10,

reducing the latency of DAC X by one cycle and aligning

its output with DAC Y, as shown in Figure 15b.

Note that variations in system temperature or supply

voltage may cause the phase of the data clock (DCKIP/N)

and sample clock (CKP/N) to vary with time. When using

the LTC2000 with SYNC_MSYN = 1, it is recommended

that users monitor SYNC_PH and adjust SYNC_PS using

Tables 12 or 13 as needed to maintain proper alignment.

Thesynchronizationproceduresdescribedabovealsowork

for systems with more than two DACs. Simply determine

the minimum DCKIP/N to CKP/N delay of all DACs by

reading SYNC_PH, and then adjust the SYNC_PS settings

to subtract one cycle of latency to those DACs whose

DCKIP/N to CKP/N delays are at least 0.4 cycles more

than the minimum. Sample verilog code implementing

the synchronization of multiple LTC2000s using Tables 12

and 13 can be found at:

http://www.linear.com/docs/44845

DBP/N[15:0]

DAC X

DCKIP/N

DAC X

IOUTP/N

DAC X

IOUTP/N

(ADJUSTED)

DAC Y

IOUTP/N

DAC Y

DCKIP/N

CKP/N

N+1

N+2

N+3

N+4

N+5

N+6

N+7

N+8

N+9

0.8 CYCLES

0.1 CYCLES

7.5 CYCLES

2000 F15b

N+2

N+1

N+2

N+1

6.5 CYCLES

7.5 CYCLES

Figure 15b. Sample Waveforms — Synchronizing Multiple LTC2000s in Single Port Mode

LTC2000 датащи(PDF) 39 Page - Linear Technology

LTC2000 датащи(HTML) 39 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

датащи скачать

ссылки URL