6

LTC1659

CLK (Pin 1): Serial Interface Clock. Internal Schmitt trig-

ger on this input allows direct optocoupler interface.

latched into the shift register on the rising edge of the serial

clock.

CS/LD (Pin 3): Serial Interface Enable and Load Control.

When CS/LD is low the CLK signal is enabled, so the data

can be clocked in. When CS/LD is pulled high, data is

loaded from the shift register into the DAC register,

updating the DAC output and the CLK is disabled

internally.

Valid on the Rising Edge of the Serial Clock.

GND (Pin 5): Ground.

The output will swing from 0V to REF. The typical input

resistance is 28k.

Requires a bypass capacitor to ground.

I

DAGRA

BLOCK

DAC

REGISTER

LD

12-BIT

SHIFT

REGISTER

POWER-ON

RESET

1659 BD

CLK 1

7

REF

6

GND

5

8

3

CS/LD

12-BIT

DAC

+

–