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LTC1659CS8 датащи(PDF) 4 Page - Linear Technology |
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LTC1659CS8 датащи(HTML) 4 Page - Linear Technology |
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4 / 12 page ![]() 4 LTC1659 Note 3: Load is 5k Ω in parallel with 100pF. Note 4: DAC switched between all 1s and the code corresponding to VOS for the part. Note 5: Digital inputs at 0V or VCC. Note 6: VOUT can only swing from (GND + VOS) to (VCC – VOS) when output is unloaded. Note 7: Guaranteed by design. Not subject to test. The q denotes specifications which apply over the full operating temperature range. Note 1: The LTC1659CMS8 is designed, characterized and expected to meet industrial temperature limits, but is not tested at – 40 °C and 85°C. Consult factory for guaranteed I-grade MSOP parts. However, these parts are guaranteed for commercial temperature limits of 0 °C to 70°C. Note 2: Nonlinearity is defined from code 20 to code 4095 (full scale). See Applications Information. VCC = 2.7V to 5.5V, VOUT unloaded, REF ≤ VCC, TA = TMIN to TMAX, unless otherwise noted. ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Switching (VCC = 4.5 to 5.5V) t1 DIN Valid to CLK Setup q 40 ns t2 DIN Valid to CLK Hold q 0ns t3 CLK High Time (Note 7) q 40 ns t4 CLK Low Time (Note 7) q 40 ns t5 CS/LD Pulse Width (Note 7) q 50 ns t6 LSB CLK to CS/LD (Note 7) q 40 ns t7 CS/LD Low to CLK (Note 7) q 20 ns t8 DOUT Output Delay CLOAD = 15pF q 5 150 ns t9 CLK Low to CS/LD Low (Note 7) q 20 ns Switching (VCC = 2.7 to 5.5V) t1 DIN Valid to CLK Setup q 60 ns t2 DIN Valid to CLK Hold q 0ns t3 CLK High Time (Note 7) q 60 ns t4 CLK Low Time (Note 7) q 60 ns t5 CS/LD Pulse Width (Note 7) q 80 ns t6 LSB CLK to CS/LD (Note 7) q 60 ns t7 CS/LD Low to CLK (Note 7) q 30 ns t8 DOUT Output Delay CLOAD = 15pF q 10 220 ns t9 CLK Low to CS/LD Low (Note 7) q 30 ns |
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