LTC1594CS datasheet(16/24 Pages) LINER

16 / 24 page

LTC1594/LTC1598

15948fb

APPLICATIONS INFORMATION

edge, the S & H goes into hold mode and the conversion

begins. The voltage on the “COM” input must remain

constant and be free of noise and ripple throughout the

conversion time. Otherwise, the conversion operation

may not be performed accurately. The conversion time is

12 CLK cycles. Therefore, a change in the “COM” input

voltage during this interval can cause conversion errors.

For a sinusoidal voltage on the “COM” input this error

would be:

VERROR(MAX) = VPEAK(2π)(f)(“COM”)12/fCLK

Where f(“COM”) is the frequency of the “COM” input

voltage, VPEAK is its peak amplitude and fCLK is the

frequency of the CLK. In most cases VERROR will not be

significant. For a 60Hz signal on the “COM” input to

generate a 1/4LSB error (305

μV) with the converter

running at CLK = 320kHz, its peak value would have to be

8.425mV.

ANALOG INPUTS

Because of the capacitive redistribution A/D conversion

techniques used, the analog inputs of the LTC1594/

LTC1598 have capacitive switching input current spikes.

These current spikes settle quickly and do not cause a

problem. However, if large source resistances are used

or if slow settling op amps drive the inputs, care must be

taken to insure that the transients caused by the current

spikes settle completely before the conversion begins.

“Analog” Input Settling

The input capacitor of the LTC1594/LTC1598 is switched

onto the selected channel input during the tSMPL time (see

Figure 7) and samples the input signal within that time. The

sample phase is at least 1 1/2 CLK cycles before conver-

sion starts. The voltage on the “analog” input must settle

completely within tSMPL. Minimizing RSOURCE+ and C1 will

improve the input settling time. If a large “analog” input

source resistance must be used, the sample time can be

increased by using a slower CLK frequency.

“COM” Input Settling

At the end of the tSMPL, the input capacitor switches to the

“COM” input and conversion starts (see Figures 1 and 7).

During the conversion, the “analog” input voltage is

effectively “held” by the sample-and-hold and will not

affect the conversion result. However, it is critical that the

“COM” input voltage settles completely during the first

CLK cycle of the conversion time and be free of noise.

Minimizing RSOURCE– and C2 will improve settling time.

If a large “COM” input source resistance must be used,

the time allowed for settling can be extended by using a

slower CLK frequency.

Input Op Amps

When driving the analog inputs with an op amp it is

important that the op amp settle within the allowed time

(see Figure 7). Again, the “analog” and “COM” input

sampling times can be extended as described above to

accommodate slower op amps. Most op amps, including

the LT

®1006 and LT1413 single supply op amps, can be

made to settle well even with the minimum settling

windows of 4.8

μs (“analog” input) which occur at the

maximum clock rate of 320kHz.

Source Resistance

The analog inputs of the LTC1594/LTC1598 look like a

20pF capacitor (CIN) in series with a 500Ω resistor (RON)

and a 45

Ω channel resistance as shown in Figure 8.

CIN gets switched between the selected “analog” and

“COM” inputs once during each conversion cycle. Large

external source resistors and capacitances will slow the

settling of the inputs. It is important that the overall RC

time constants be short enough to allow the analog

inputs to completely settle within the allowed time.

Figure 8. Analog Input Equivalent Circuit

RON

500

RON

CIN

20pF

LTC1594

LTC1598

“ANALOG”

INPUT

RSOURCE+

VIN+

“COM”

INPUT

MUXOUT

MUX

ADCIN

RSOURCE–

VIN–

1594/98 • F08

LTC1594CS датащи(PDF) 16 Page - Linear Technology

LTC1594CS датащи(HTML) 16 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL