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LTC1436A

LTC1436A-PLL/LTC1437A

APPLICATIONS INFORMATION

An internal 3

µA current source charges up an external

capacitor CSS. When the voltage on RUN/SS reaches 1.3V

the LTC1436A/LTC1437A begin operating. As the voltage

on RUN/SS continues to ramp from 1.3V to 2.4V, the

internal current limit is also ramped at a proportional linear

rate. The current limit begins at approximately 50mV/

RSENSE (at VRUN/SS = 1.3V) and ends at 150mV/RSENSE

(VRUN/SS > 2.7V). The output current thus ramps up

slowly, charging the output capacitor. If RUN/SS has been

pulled all the way to ground there is a delay before starting

of approximately 500ms/

µF, followed by an additional

500ms/

µF to reach full current.

tDELAY = 5(105)CSS seconds

Pulling the RUN/SS pin below 1.3V puts the LTC1436A/

LTC1437A into a low quiescent current shutdown (IQ <

µA). This pin can be driven directly from logic as shown

in Figure 6. Diode D1 in Figure 6 reduces the start delay but

allows CSS to ramp up slowly for the soft start function;

this diode and CSScan be deleted if soft start is not needed.

The RUN/SS pin has an internal 6V Zener clamp (see

Functional Diagram).

Foldback current limiting is implemented by adding a

diode DFB between the output and ITH pins as shown in the

Function Diagram. In a hard short (VOUT = 0V), the current

will be reduced to approximately 25% of the maximum

output current. This technique may be used for all applica-

tions with regulated output voltages of 1.8V or greater.

Phase-Locked Loop and Frequency Synchronization

The LTC1436A-PLL/LTC1437A each have an internal volt-

age-controlled oscillator and phase detector comprising a

phase-locked loop. This allows the top MOSFET turn-on to

be locked to the rising edge of an external source. The

frequency range of the voltage-controlled oscillator is

±30% around the center frequency fO.

The value of COSC is calculated from the desired operating

frequency fO. Assuming the phase-locked loop is locked

(VPLLLPF = 1.19V):

Frequency

OSC pF

kHz

()=

()













21 10

)

–

Stating the frequency as a function of VPLLLPF and COSC:

Frequency kHz

CpF

OSC

PLLLPF

()=

()+

[]





















84 10

2000

)

µµ

The phase detector used is an edge sensitive digital type

which provides zero degrees phase shift between the

external and internal oscillators. This type of phase detec-

tor will not lock up on input frequencies close to the

harmonics of the VCO center frequency. The PLL hold-in

range

∆fH is equal to the capture range: ∆fH = ∆fC =

±0.3fO.

Foldback Current Limiting

As described in Power MOSFET and D1 Selection, the

worst-case dissipation for either MOSFET occurs with a

short-circuited output, when the synchronous MOSFET

conducts the current limit value almost continuously. In

most applications this will not cause excessive heating,

even for extended fault intervals. However, when heat

sinking is at a premium or higher RDS(ON) MOSFETs are

being used, foldback current limiting should be added to

reduce the current in proportion to the severity of the fault.

1436 F06

CSS

3.3V OR 5V

RUN/SS

CSS

RUN/SS

Figure 6. Run/SS Pin Interfacing

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