LTC1436A datasheet(10/28 Pages) LINER

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LTC1436A

LTC1436-PLL-A/LTC1437A

OPERATIO (Refer to Functional Diagram)

Main Control Loop

The LTC1436A/LTC1437A use a constant frequency, cur-

rent mode step-down architecture. During normal opera-

tion, the top MOSFET is turned on each cycle when the

oscillator sets the RS latch and turned off when the main

current comparator I1 resets the RS latch. The peak

inductor current at which I1 resets the RS latch is con-

trolled by the voltage on ITHpin, which is the output of error

amplifier EA. VPRGM and VOSENSEpins, described in the Pin

Functions, allow EA to receive an output feedback voltage

VFB from either internal or external resistive dividers. When

the load current increases, it causes a slight decrease in

VFB relative to the 1.19V reference, which in turn causes the

ITH voltage to increase until the average inductor current

matches the new load current. While the top MOSFET is off,

the bottom MOSFET is turned on until either the inductor

current starts to reverse, as indicated by current compara-

tor I2, or the beginning of the next cycle.

The top MOSFET drivers are biased from floating boot-

strap capacitor CB, which normally is recharged during

each off cycle. However, when VIN decreases to a voltage

close to VOUT, the loop may enter dropout and attempt to

turn on the top MOSFET continuously. The dropout detec-

tor counts the number of oscillator cycles that the top

MOSFET remains on, and periodically forces a brief off

period to allow CB to recharge.

The main control loop is shut down by pulling RUN/SS pin

low. Releasing RUN/SS allows an internal 3

µA current

source to charge soft start capacitor CSS. When CSS

reaches 1.3V, the main control loop is enabled with the ITH

voltage clamped at approximately 30% of its maximum

value. As CSS continues to charge, ITH is gradually re-

leased allowing normal operation to resume.

Comparator OV guards against transient overshoots

> 7.5% by turning off the top MOSFET and keeping it off

until the fault is removed.

Low Current Operation

Adaptive Power mode allows the LTC1436A/LTC1437A to

automatically change between two output stages sized for

different load currents. TGL and BG pins drive large

synchronous N-channel MOSFETs for operation at high

currents, while the TGS pin drives a much smaller

N-channel MOSFET used in conjunction with a Schottky

diode for operation at low currents. This allows the loop to

continue to operate at normal frequency as the load

current decreases without incurring the large MOSFET

gate charge losses. If the TGS pin is left open, the loop

defaults to Burst Mode operation in which the large

MOSFETs operate intermittently based on load demand.

Adaptive Power mode provides constant frequency opera-

tion down to approximately 1% of rated load current. This

results in an order of magnitude reduction of load current

before Burst Mode operation commences. Without the

small MOSFET (i.e.: no Adaptive Power mode), the transi-

tion to Burst Mode operation is approximately 10% of

rated load current.

The transition to low current operation begins when com-

parator I2 detects current reversal and turns off the

bottom MOSFET. If the voltage across RSENSE does not

exceed the hysteresis of I2 (approximately 20mV) for one

full cycle, then on following cycles the top drive is routed to

the small MOSFET at TGS pin and BG pin is disabled. This

continues until an inductor current peak exceeds 20mV/

RSENSE or the ITH voltage exceeds 0.6V, either of which

causes drive to be returned to TGL pin on the next cycle.

Two conditions can force continuous synchronous opera-

tion, even when the load current would otherwise dictate

low current operation. One is when the common mode

voltage of the SENSE + and SENSE – pins is below 1.4V and

the other is when the SFB pin is below 1.19V. The latter

condition is used to assist in secondary winding regulation

as described in the Applications Information section.

Frequency Synchronization

A Phase-locked loop (PLL) is available on the

LTC1436A-PLL and LTC1437A to allow the oscillator to be

synchronized to an external source connected to the

PLLIN pin. The output of the phase detector at the PLL LPF

pin is also the control input of the oscillator, which

operates over a 0V to 2.4V range corresponding to – 30%

to 30% in frequency. When locked, the PLL aligns the turn-

on of the top MOSFET to the rising edge of the synchroniz-

ing signal. When PLLIN is left open or at a constant DC

voltage, PLL LPF goes low, forcing the oscillator to mini-

mum frequency.

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