LTC1409CSW datasheet(8/20 Pages) LINER

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LTC1409

APPLICATIONS INFORMATION

CONVERSION DETAILS

The LTC1409 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an

analog signal to a 12-bit parallel output. The ADC is

complete with a precision reference and an internal clock.

The control logic provides easy interface to microproces-

sors and DSPs. (Please refer to the Digital Interface

section for the data format.)

Conversion start is controlled by the CS and CONVST

inputs. At the start of the conversion the successive

approximation register (SAR) is reset. Once a conversion

cycle has begun it cannot be restarted.

During the conversion, the internal differential 12-bit

capacitive DAC output is sequenced by the SAR from the

most significant bit (MSB) to the least significant bit

(LSB). Referring to Figure 1, the +AIN and –AIN inputs are

connected to the sample-and-hold capacitors (CSAMPLE)

during the acquire phase and the comparator offset is

nulled by the zeroing switches. In this acquire phase, a

minimum delay of 150ns will provide enough time for the

sample-and-hold capacitors to acquire the analog signal.

During the convert phase the comparator zeroing switches

open, putting the comparator into compare mode. The

input switches connect the CSAMPLE capacitors to ground,

transferring the differential analog input charge onto the

summing junction. This input charge is successively com-

pared with the binary-weighted charges supplied by the

differential capacitive DAC. Bit decisions are made by the

high speed comparator. At the end of a conversion, the

differential DACs output balances the +AIN and –AIN input

charges. The SAR contents (a 12-bit data word) which

represents the difference of +AIN and –AIN are loaded into

the 12-bit output latches.

DYNAMIC PERFORMANCE

The LTC1409 has excellent high speed sampling capabil-

ity. FFT (Fast Four Transform) test techniques are used to

test the ADC’s frequency response, distortion and noise at

the rated throughput. By applying a low distortion sine

wave and analyzing the digital output using FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. Figure 2 shows typical

LTC1409 plots.

Figure 1. Simplified Block Diagram

COMP

+CSAMPLE

–CDAC

•

D11

ZEROING SWITCHES

HOLD

+AIN

–AIN

+CDAC

–CSAMPLE

LTC1409 • F01

–

SAR

OUTPUT

LATCHES

+VDAC

–VDAC

HOLD

Figure 2b. LTC1409 Nonaveraged, 4096 Point FFT,

Input Frequency = 375kHz

FREQUENCY (kHz)

100

200

300

400

LT1409 • F02b

–20

–40

–60

–80

–100

–120

150

250

350

fSAMPLE = 800kHz

fIN = 375kHz

SFDR = 89dB

SINAD = 72.5dB

Figure 2a. LTC1409 Nonaveraged, 4096 Point FFT,

Input Frequency = 100kHz

FREQUENCY (kHz)

100

200

300

400

LT1409 • F02a

–20

–40

–60

–80

–100

–120

150

250

350

fSAMPLE = 800kHz

fIN = 97.45kHz

SFDR = 89.1dB

SINAD = 73.1dB

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