4

LTC1401

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Maximum Sampling Frequency

q

200

kHz

Conversion Time

q

4.1

µs

Acquisition Time

315

ns

CLK Frequency

q

0.1

3.2

MHz

CLK Pulse Width

(Note 6)

q

60

ns

Time to Wake Up from Nap Mode

350

ns

CLK Pulse Width to Return to Active Mode

q

60

ns

CONV

↑ to CLK↑ Setup Time

q

100

ns

CONV

↑ After Leading CLK↑

q

0ns

CONV Pulse Width

(Note 8)

q

50

ns

Time from CLK

↑ to Sample Mode

80

ns

Aperture Delay of Sample-and-Hold

Jitter < 50ps

45

ns

Minimum Delay Between Conversion

(Note 6)

q

350

550

ns

Delay Time, CLK

q

60

120

ns

Delay Time, CLK

q

60

120

ns

Time from Previous Data Remains Valid After CLK

↑

q

15

50

ns

(Note 5)

TI I G CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to GND.

will be clamped by internal diodes. This product can handle input currents

greater than 40mA without latch-up if the pin is driven below GND or

Note 4: When these pin voltages are taken below GND, they will be clamped

by internal diodes. This product can handle input currents greater than 40mA

without latch-up if the pin is driven below GND. These pins are not clamped

specified.

Note 6: Guaranteed by design, not subject to test.

Note 7: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 8: The rising edge of CONV starts a conversion. If CONV returns low

at a bit decision point during the conversion, it can create small errors. For

best performance, ensure that CONV returns low either within 120ns after

the conversion starts (i.e., before the first bit decision) or after the 14

clock cycles. (Figure 13 Timing Diagram).