LTC1401CS8 datasheet(12/20 Pages) LINER

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LTC1401

APPLICATIONS INFORMATION

circuitry. In this mode, the ADC draws only 1.5mW of

power instead of 15mW (for minimum power, the logic

inputs must be within 500mV of the supply rails). The

wake-up time from Nap mode to active mode is 350ns. In

Sleep mode, power consumption is reduced to 19.5

µW by

cutting off the supply to the comparator and reference.

Figure 11 illustrates power-down methods for the LTC1401.

The chip enters Nap mode by keeping the CLK signal low

and pulsing the CONV signal twice. For Sleep mode

operation, CONV signal should be pulsed four times while

CLK is kept low. NAP and SLEEP modes are activated on

the falling edge of the CONV pulse. By pulling SHDN low,

the LTC1401 enters Shutdown mode and power con-

sumption drops to 13.5

µW.

Once SHDN goes high, the LTC1401 returns to active

mode or the LTC1401 returns to active mode by pulsing

the CLK signal if the device has entered Nap/Sleep mode.

During the transistion from Sleep mode to active mode,

the VREF voltage ramp-up time is a function of its loading

conditions. With a 10

µF bypass capacitor, the wake-up

time from Sleep mode is typically 3ms. A REFRDY signal

is activated once the reference has settled and is ready for

an A/D conversion. This REFRDY bit is sent to the DOUT pin

as the first bit followed by the 12-bit data word (refer to

Figure 12).

DIGITAL INTERFACE

The digital interface requires only three digital lines. CLK

and CONV are both inputs, and the DOUT output provides

the conversion result in serial form.

Figures 12 and 13 show the digital timing waveform of the

LTC1401 during the Analog to Digital Conversion. The

CONV rising edge starts the conversion. Once initiated, it

can not be restarted until the conversion is completed. If

the time from the CONV signal to the CLK rising edge is

less than t2, the digital output will be delayed by one clock

cycle.

The digital output data is updated on the rising edge of the

CLK line. The digital output data consists of a REFRDY bit

followed by the valid 12-bit data word. DOUT data should

be captured by the receiving system on the rising CLK

edge. Data remains valid for a minimum time of t10 after

the rising CLK edge to allow capture to occur.

Figure 11. Nap Mode and Sleep Mode Waveforms

CLK

CONV

NAP

SLEEP

VREF

REFRDY

NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS THE FIRST BIT IN THE DOUT WORD.

LTC1401 • F11

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