LTC1279CSW datasheet(8/16 Pages) LINER

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LTC1279

TEST CIRCUITS

Load Circuits for Output Float Delay

Load Circuits for Access Timing

DBN

DGND

A) HIGH-Z TO VOH (t8)

AND VOL TO VOH (t6)

DBN

B) HIGH-Z TO VOL (t8)

AND VOH TO VOL (t6)

DGND

1279 TC01

10pF

DBN

DGND

A) VOH TO HIGH-Z

10pF

DBN

B) VOL TO HIGH-Z

DGND

1279 TC02

CS to RD Setup Timing

SHDN to CONVST Wake-Up Timing

CS to CONVST Setup Timing

TI I G DIAGRA S

APPLICATIONS INFORMATION

CONVERSION DETAILS

The LTC1279 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an

analog signal to a 12-bit parallel output. The ADC is

complete with a precision reference and an internal clock.

The control logic provides easy interface to microproces-

sors and DSPs. (Please refer to the Digital Interface

section for the data format.)

Conversion start is controlled by the CS and CONVST

inputs. At the start of conversion the successive approxi-

mation register (SAR) is reset. Once a conversion cycle

has begun it cannot be restarted.

During conversion, the internal 12-bit capacitive DAC

output is sequenced by the SAR from the most significant

bit (MSB) to the least significant bit (LSB). Referring to

Figure 1, the AIN input connects to the sample-and-hold

capacitor during the acquire phase, and the comparator

offset is nulled by the feedback switch. In this acquire

phase, a minimum delay of 160ns will provide enough

VDAC

1279 F01

–

CDAC

DAC

SAMPLE

HOLD

CSAMPLE

12-BIT

LATCH

COMPAR-

ATOR

SAMPLE

AIN

Figure 1. AIN Input

SHDN

CONVST

1279 TD03

1279 TD01

CONVST

1279 TD02

time for the sample-and-hold capacitor to acquire the

analog signal. During the convert phase, the comparator

feedback switch opens, putting the comparator into the

compare mode. The input switch switches CSAMPLE to

ground, injecting the analog input charge onto the sum-

ming junction. This input charge is successively com-

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