19

LTC1274/LTC1277

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

S

APPLICATI

I FOR ATIO

The LTC1277 has an additional Nap mode. When NAP

(Pin 7) is tied low, all the power is off except the internal

reference which is still active and provides 2.42V output

voltage to the other circuitry. In this mode the ADC draws

0.9mW instead of 10mW (for minimum power, the logic

inputs must be within 600mV from the supply rails). The

wake-up time from the power shutdown to active state is

620ns. The typical performance graph on the front page of

this data sheet shows that the power will be reduced

greatly by using the Sleep and Nap modes.

Power Shutdown

The LTC1274/LTC1277 provide shutdown features that

will save power when the ADC is in inactive periods. Both

ADCs have a Sleep mode. To power down the ADCs,

SLEEP (Pin 18 in LTC1274 or Pin 6 in LTC1277) needs to

be driver low. When in Sleep mode, the LTC1274/LTC1277

will not start a conversion even though the CONVST goes

low. The parts draw 1

µA. After release from the Sleep

mode, the ADCs need 3ms (4.7

µF bypass capacitor on

to indicate the ADC is ready to do conversions.

RD = CONVST

BUSY

LTC1274/77 • F16

CS = 0

HBEN (LTC1277)

DATA N

DB11 TO DB0

DATA N

DB7 TO DB0

DATA (N – 1)

DB7 TO DB0

DATA (N – 1)

DB11 TO DB0

DATA N

DB11 TO DB8

LTC1274 DATA

LTC1277 DATA

(SAMPLE N)

DATA (N + 1)

DB7 TO DB0

DATA N

DB11 TO DB0

DATA (N + 1)

DB11 TO DB8

(SAMPLE N + 1)

DATA (N + 1)

DB11 TO DB0

DATA N

DB11 TO DB0

Figure 16. Slow Memory Mode

RD = CONVST

BUSY

LTC1274/77 • F17

CS = 0

HBEN (LTC1277)

DATA (N – 1)

DB11 TO DB0

DATA (N – 1)

DB7 TO DB0

DATA (N – 1)

DB11 TO DB8

LTC1274 DATA

LTC1277 DATA

(SAMPLE N)

DATA N

DB7 TO DB0

DATA N

DB11 TO DB8

(SAMPLE N + 1)

DATA N

DB11 TO DB0

Figure 17. ROM Mode Timing