LTC1277CS datasheet(16/20 Pages) LINER

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LTC1274/LTC1277

APPLICATI

I FOR ATIO

LTC1274

LTC1277

AIN (LTC1274)

AIN

+ (LTC1277)

AGND

AIN

– (LTC1277)

LTC1274/77 F11a

100

Ω

FULL-SCALE

ADJUST

10k

Ω

–

ADDITIONAL PINS OMITTED FOR CLARITY

±20LSB TRIM RANGE

LTC1274/77 F11b

10k

100k

10k

Ω

ANALOG

INPUT

0V TO

4.096V

100k

10k

OFFSET

ADJUST

400

Ω

4.3k

FULL-SCALE

ADJUST

100k

–

LTC1274

LTC1277

AIN (LTC1274)

AIN

+ (LTC1277)

AIN

– (LTC1277)

Figure 11a. Full-Scale Adjust Circuit

Figure 11b. LTC1274/LTC1277 Unipolar Offset and

Full-Scale Adjust Circuit

Figure 11c. LTC1274/LTC1277 Bipolar Offset and

Full-Scale Adjust Circuit

adjusted before full-scale error. Bipolar offset error ad-

justment is achieved by trimming the offset adjust while

the input voltage is 0.5LSB below ground. This is done by

applying an input voltage of – 0.50mV (– 0.5LSB) to the

input in Figure 11c and adjusting the R8 until the ADC’s

output code flickers between 0000 0000 0000 and 1111

1111 1111 in LTC1274 or between 0111 1111 1111 and

1000 0000 0000 in LTC1277. For full-scale adjustment, an

input voltage of 2.0465V (FS – 1.5LSBs) is applied to the

input and R5 is adjusted until the output code flickers

between 0111 1111 1110 and 0111 1111 1111 in LTC1274

or between 1111 1111 1110 and 1111 1111 1111 in

LTC1277.

Internal Clock

The A/D converters have an internal clock that eliminates

the need of synchronization between the external clock

and the CS and RD signals found in other ADCs. The

internal clock is factory trimmed to achieve a typical

conversion time of 6

µs. No external adjustments are

required and with the maximum acquisition time of 2

µs

throughput performance of 100ksps is assured.

Timing and Control

Conversion start and data read operations are controlled

by three digital inputs in the LTC1274: CS, CONVST and

RD. For the LTC1277 there are four digital inputs: CS,

CONVST, RD and HBEN. Figure 12 shows the logic

structure associated with these inputs for LTC1277. A

falling edge on CONVST will start a conversion after the

ADC has been selected (i.e., CS is low). Once initiated, it

cannot be restarted until the conversion is complete.

Converter status is indicated by the BUSY output and this

is low while conversion is in progress. The High Byte

Enable input (HBEN) in the LTC1277 is to multiplex the 12

bits of conversion data onto the lower D7 to D0/8

outputs.

Figures 13 through 17 show several different modes of

operation. In modes 1a and 1b (Figures 13 and 17) CS and

RD are both tied low. The falling edge of CONVST starts the

conversion. The data outputs are always enabled and data

can be latched with the BUSY rising edge. Mode 1a shows

operation with a narrow logic low CONVST pulse. Mode 1b

shows a narrow logic high CONVST pulse.

LTC1274/77 F11c

10k

100k

10k

ANALOG

INPUT

100k

20k

OFFSET

ADJUST

200

Ω

4.3k

FULL-SCALE

ADJUST

100k

–

–5V

LTC1274

LTC1277

AIN (LTC1274)

AIN

+ (LTC1277)

AIN

– (LTC1277)

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