5

LTC1096L/LTC1098L

PI FU CTIO S

CH1 (Pin 3): Analog Input. This input must be free of noise

with respect to GND.

GND (Pin 4): Analog Ground. GND should be tied directly

to an analog ground plane.

shifted into this pin.

result is shifted out of this output.

CLK (Pin 7): Shift Clock. This clock synchronizes the serial

data transfer.

vides power and defines the span of the A/D converter. It

must be free of noise and ripple by bypassing directly to

the analog ground plane

TEST CIRCUITS

1.4V

3k

100pF

TEST POINT

LTC1096/98 • TC01

LTC1096/98 • TC02

WAVEFORM 1

(SEE NOTE 1)

90%

10%

WAVEFORM 2

(SEE NOTE 2)

CS

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.

LTC1096/98 • TC04

3k

100pF

TEST POINT

LTC1096/98 • TC03

CLK

LTC1096/98 • TC05