5

LT1573

activated by applying a voltage > 1.3V to the SHDN pin. The

output voltage will restart as soon as the SHDN pin is

pulled below the shutdown threshold. If the shutdown/

reset function is not used, the pin should be grounded. The

voltage applied to the SHDN pin can be higher than the

input voltage. When the SHDN pin voltage is higher than

2V, the SHDN pin current increases and is limited by an

internal 20k resistor.

GND (Pin 4): Circuit Ground.

DRIVE (Pin 5): The DRIVE pin is connected to the collector

of the main drive transistor of the LT1573. This drive

transistor sinks the base current of the external PNP

output transistor. A resistor is normally inserted between

the base of the external PNP output transistor and the

DRIVE pin. This resistor is sized to allow the LT1573 to

sink the appropriate amount of base current for a given

application and to activate the overcurrent latch in a fault

condition.

of the LT1573 including bias, start-up, thermal limit, error

amplifier and all overcurrent latch circuitry.

shown in Block Diagram. This pin is normally connected

to the output. The comparator C1 is used to disable the

overcurrent latch during start-up when the output transis-

tor is saturated. For fixed voltage devices the top of the

internal resistor divider that sets the output voltage is

connected to this pin.

COMP (Pin 8): A compensation network is inserted

transient response. Under normal condition, the DC volt-

FB (Pin 1): The feedback pin is the inverting input of the

error amplifier. The noninverting input of the error ampli-

fier is internally connected to a 1.265V reference. The error

in Figure 1, to force the voltage at the feedback pin to be

1.265V. Output voltage is set by a resistor divider as

shown in Figure 1. For adjustable devices an external

resistor divider is used to set the output voltage. For fixed

voltage devices the resistor divider is internal and the top

LATCH (Pin 2): The LT1573 provides overcurrent protec-

tion with a timed latch-off circuit. The latch-off time out is

triggered when the DRIVE pin is pulled below the satura-

tion voltage of the drive transistor. The saturation voltage

is a function of the drive current and is equal to approxi-

mately 130mV at 20mA rising to 780mV at 250mA (see

typical performance curves). The time out is set by the

latch charging current and the value of a capacitor con-

nected between the LATCH pin and ground. If the

overcurrent condition persists at the end of the timing

cycle the regulator will latch off until either the latch is reset

or power is cycled off and back on. The latch can be reset

by either pulling the SHDN pin high, pulling current out of

the LATCH pin greater than latching current or grounding

the LATCH pin. Exceeding the thermal limit temperature

will trigger the latch with no timing delay. Under normal

condition, the DC voltage at the LATCH pin is zero. When

the system is latched off, the DC voltage at theLATCH pin

SHDN (Pin 3): The SHDN pin has two functions. It can be

used to turn off the output voltage by disabling the drive to

the output transistor. It can also be used to reset the

current limit latch. The shutdown/reset functions are

PI FU CTIO S