LT1507CS8 datasheet(18/20 Pages) LINER

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LT1507

APPLICATIONS INFORMATION

Example: with VIN = 5V, VOUT = 3.3V, IOUT = 1A;

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04 1 3 3

16 10

1 5 500 10

026 0 04

0 008

0 046

5 0 003

3 3 0 005

0 032

Total power dissipation is 0.3 + 0.046 + 0.032 = 0.38W.

Thermal resistance for the LT1507 packages is influenced

by the presence of internal or backside planes. With a full

plane under the SO package, thermal resistance will be

about 120

°C/W. No plane will increase resistance to about

150

°C/W. To calculate die temperature, use the proper

thermal resistance number for the desired package and

add in worst-case ambient temperature;

TJ = TA + θJA(PTOT)

With the S8 package (

θJA = 120°C/W) at an ambient

temperature of 70

°C;

TJ = 70 + 120(0.38) = 116°C

FREQUENCY COMPENSATION

The LT1507 uses a “current mode” architecture to help

alleviate phase shift created by the inductor. The basic

connections are shown in Figure 9. Gain of the power stage

can be modeled as 1.8A/V transconductance from the VC

pin voltage to current delivered to the output. This is

shown in Figure 8 where the transconductance from VC

pin to inductor current is essentially flat from 50Hz to

50kHz and phase shift is minimal in the important loop

unity-gain band of 1kHz to 50kHz. Inductor variation from

µH to 20µH will have very little effect on these curves.

Overall gain from the VC pin to output is then modeled as

the product of 1.8A/V transconductance multiplied by the

complex impedance of the load in parallel with the output

capacitor model.

The error amplifier can be modeled as a transconductance

of 2000

µmho, with an output impedance of 200kΩ in

FREQUENCY (Hz)

2.0

1.5

1.0

0.5

–40

–80

10k

100k

LT1507 • F08

100

GAIN (A/V)

PHASE

VOUT = 3.3V

IOUT = 250mA

VIN = 5V

L = 10

µH

Figure 8. Phase and Gain from VC Pin Voltage

to Inductor Current

POWER STAGE

gm = 1.8A/V

ERROR AMPLIFIER

gm = 2000µho

200k

2.42V

LT1507

GND

VSW

ESR

OUTPUT

1507 • F09

12pF

Figure 9. Small-Signal Model for Loop Stability Analysis

parallel with 12pF. In all practical applications, the com-

pensation network from VC pin to ground has a much

lower impedance than the output impedance of the ampli-

fier at frequencies above 500Hz. This means that the error

amplifier characteristics themselves do not contribute

excess phase shift to the loop and the phase/gain charac-

teristics of the error amplifier section are completely

controlled by the external compensation network.

The complete small-signal model is shown in Figure 9. R1

and R2 are the divider used to set output voltage. These are

internal on the fixed voltage LT1507-3.3 with R1 = 1.8k

and R2 = 5k. RC, CC and CF are external compensation

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