LT1432CS8 datasheet(8/28 Pages) LINER

8 / 28 page

LT1432

APPLICATI

I FOR ATIO

FET Switch Loss

IN – OUT

OUT

= ()(

)( )

(Ignoring gate drive power)

The change in efficiency is:

Diode Loss – FET Loss Efficiency

OUT

()(

)

()( )

This is equal to:

V– V

V – R

OUT

FET

OUT

()

()( )

If VF (diode forward voltage) = 0.45V, VIN = 10V, VOUT = 5V,

RFET = 0.1Ω, IOUT = 1A, and efficiency = 90%, the improve-

ment in efficiency is only:

10V – 5V 0.45V – 0.1

1A 0.9

10V 5V

2.8%

()

()( )

Ω

This does not take FET gate drive losses into account,

which can easily reduce this figure to less than 2%. The

added cost, size, and complexity of a synchronous switch

configuration would be warranted only in the most ex-

treme circumstances.

Burst mode efficiency is limited by quiescent current drain

in the LT1432 and the switching IC. The typical burst mode

zero-load input power is 27mW. This gives about one

month battery life for a 12V, 1.2AHr battery pack. Increas-

ing load power reduces discharge time proportionately.

Full shutdown current is only about 15

µA, which is consid-

erably less than the self-discharge rate of typical batteries.

Burst Mode Operation

Burst mode is initiated by allowing the mode pin to float,

where it will assume a DC voltage of approximately 1V. If

AC pickup from surrounding logic lines is likely, the mode

pin should be bypassed with a 200pF capacitor. Burst

mode is used to reduce quiescent operating current when

the regulator output current is very low, as in “sleep” mode

in a lap-top computer. In this mode, hysteresis is added to

the error amplifier to make it switch on and off, rather than

maintain a constant amplifier output. This forces the

switching IC to either provide a rapidly increasing current

or to go into full micropower shutdown. Current is deliv-

ered to the output capacitor in pulses of higher amplitude

and low duty cycle rather than a continuous stream of low

amplitude pulses. This maximizes efficiency at light load

by eliminating quiescent current in the switching IC during

the period between bursts.

The result of pulsating currents into the output capacitor

is that output ripple amplitude increases, and ripple fre-

quency becomes a function of load current. The typical

output ripple in burst mode is 150mVp-p, and ripple

frequency can vary from 50Hz to 2kHz. This is not normally

a problem for the logic circuits which are kept “alive”

during sleep mode.

Some thought must be given to proper sequencing be-

tween normal mode and burst mode. A heavy (>100mA)

load in burst mode can cause excessive output ripple, and

an abnormally light load (10mA to 30mA, see curves) in

normal mode can cause the regulator to revert to a quasi-

burst mode that also has higher output ripple. The worst

condition is a sudden, large increase in load current

(>100mA) during this quasi-burst mode or just after a

switch from burst mode to normal mode. This can cause

the output to sag badly while the regulator is establishing

normal mode operation (

≈100µs). To avoid problems, it is

suggested that the power-down sequence consist of re-

ducing load current to below 100mA, but greater than the

minimum for normal mode, then switching to burst mode,

followed by a reduction of load current to the final sleep

value. Power-up would consist of increasing the load

current to the minimum for normal mode, then switching

to normal mode, pausing for 1ms, followed by return to

full load.

If this sequence is not possible, an alternative is to

minimize normal mode settling time by adding a 47k

Ω

resistor between V

+ and V

C pins. The output capacitor

should be increased to >680

µF and the compensation

capacitors should also be as small as possible, consistent

with adequate phase margin. These modifications will

LT1432CS8 датащи(PDF) 8 Page - Linear Technology

LT1432CS8 датащи(HTML) 8 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

датащи скачать

ссылки URL