Peripheral migration guide

AN4658

14/24

DocID027496 Rev 1

2.7

RTC

The STM32F446 and STM32F429/439 lines implement the same features on the RTC, as

shown in Table 9.

I2S

Clock source for I2S on APB1

PLLI2SCLK

PLLI2SCLK

I2S_CKIN

I2S_CKIN

HSE/HSI

Main PLL (PLLR output clock)

Clock source for I2S on APB2

PLLI2SCLK

PLLI2SCLK

I2S_CKIN

NA

HSE/HSI

Main PLL (PLLR output clock)

SAI1

PLLSAIQ(1)

PLLSAIQ(2)

I2S_CKIN(1)

I2S_CKIN(2)

NA

Main PLL (PLLR output clock)(2)

SAI2

NA

PLLI2SQ(2)

PLLSAIQ(2)

I2S_CKIN(2)

Main PLL (PLLR output clock)(2)

SPDIF-RX

NA

Main PLL (PLLR output clock)

HDMI-CEC

NA

LSE clock

HSI clock divided by 488

1. Configurable clock per SAI sub-block.

2. Configurable clock per SAI block.

Table 8. Reset and Clock Controller comparison (continued)

RCC

STM32F429xx/439xx

STM32F446xx

Table 9. RTC comparison

RTC

STM32F429xx/439xx

STM32F446xx

Calendar in BCD

Yes

Yes

Calendar Sub seconds access

Yes

Yes

Calendar synchronization on the fly

Yes

Yes

Alarm on calendar

2 with subseconds

Calendar Calibration

Calibration window: 8s / 16s / 32s

Calibration step: 3.81ppm / 1.91ppm / 0.95 ppm

Range [-480ppm +480ppm]

Synchronization on mains

Yes

Yes