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AN4538 датащи(PDF) 7 Page - STMicroelectronics

номер детали AN4538
подробное описание детали  Power consumption optimization with STM32F3xx microcontrollers
PDF  25 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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AN4538 датащи(HTML) 7 Page - STMicroelectronics

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AN4538
STM32F3xx microcontroller low-power overview
24
Note:
For more details about the power supply, you can refer to the reference manuals RM00313,
RM0316, RM0364, RM0365, RM0366 and to the relevant datasheets available from the
STMicroelectronics web site.
1.2
Power mode features
By default, after power-on or system reset, the STM32F3xx microcontrollers are in Run
mode. This is a fully active mode that consumes much power even when performing minor
tasks.
Highly optimized low-power modes are integrated to save power when the CPU does not
need to be kept running, thus allowing to achieve the best compromise between a low-
power consumption, a short startup time and available wakeup sources in the application
design.
This part describes the different low-power modes available in STM32F3xxxx devices and
the related features.
STM32F3xxxx devices feature four main low-power modes:
Sleep mode:
Only the CPU clock is stopped.
The Cortex®-M4 clock is stopped and the peripherals are kept running. The
current consumption increases with the clock frequency. As in a Run mode, the
user needs to know the system clock configuration rules.
Stop mode
The lowest power consumption while all the SRAM and registers are kept.
PLL, HSI, HSE are disabled.
All clocks in 1.8 V domain are switched off.
Voltage regulator is working in normal mode or low-power modes.
Stop mode achieves the lowest power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE are
disabled. The voltage regulator can also be put either in normal or in low-power modes (not
available when internal regulator is off).
Table 2. STM32F3xxxx device power supply considerations
Internal regulator
status
VDD
VDDA
Power domain considerations
Voltage regulator ON
From 2V to 3.6V
From 2V to 3.6V
VDDA ≥ VDD
VDDA ≥ 2.4V
when DAC and
OPAMP are used.
VDDA ≥ 1.8V
when ADC is
used.
No
considerations
Voltage regulator OFF
1.8V ± 8%
From 1.65V to 3.6V
POR, PDR and
PVD features are
not available.
Standby mode is
not available.



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