RM0312 datasheet(231/275 Pages) STMICROELECTRONICS

231 / 275 page

DocID022352 Rev 3

231/275

RM0312

Universal synchronous/asynchronous receiver transmitter (USART)

249

Figure 84. TC/TXE behavior when transmitting

1. This example assumes that several other transmissions occurred after TE has been set. Otherwise an

IDLE preamble would be transmitted first when writing to USART_DR for the first time.

Break character

Setting the SBK bit transmits a break character. The break frame length depends on the M

bit (see Figure 82).

If the SBK bit is set to ‘1’ a break character is sent on the USART_TX line after completing

the current character transmission. This bit is reset by hardware when the break character is

completed (during the STOP bit of the break character).The USART inserts a logic 1 bit at

the end of the last break frame to guarantee the recognition of the start bit of the next frame.

Note:

The break character is sent without taking into account the number of STOP bits. If the

USART is programmed with 2 STOP bits, the Tx line is pulled low until the end of the first

STOP bit only. Then 2 logic 1 bits are inserted before the next character.

Note:

If the software resets the SBK bit before the start of break transmission, the break character

is not transmitted. For two consecutive breaks, the SBK bit should be set after the STOP bit

of the previous break.

Idle character

Setting the TEN bit drives the USART to send an idle frame before the first data frame.

21.3.3

Receiver

The USART can receive data words of either 8 or 9 bits. When the M bit is set, word length

is 9 bits and the MSB is stored in the R8 bit in the USART_CR1 register.

Start bit detection

In the USART, the start bit is detected when a specific sequence of samples is recognized.

This sequence is: 1 1 1 0 X 0 X 0X 0X 0 X 0X 0. The start bit detection sequence shown in

Figure 85.

TX line

USART_DR

Frame 1

TXE flag

TC flag

Frame 2

Software waits until TXE = 1

and writes F2 into DR

Software waits until TXE = 1

and writes F3 into DR

TC is not set

because TXE = 0

Software waits until TC = 1

Frame 3

TC is set because

TXE = 1

Set by hardware and

cleared by software

Set by hardware and

cleared by software

Set by hardware

Set

Idle preamble

by hardware

Software

enables the

USART

TC is not set

because TXE = 0

Software waits until TXE = 1

and writes F1 into DR

ai17121c

TC is cleared

by software

sequence

RM0312 датащи(PDF) 231 Page - STMicroelectronics

RM0312 датащи(HTML) 231 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL