RM0312 datasheet(229/275 Pages) STMICROELECTRONICS

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RM0312

Universal synchronous/asynchronous receiver transmitter (USART)

249

21.3.2

Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status.

When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the

T8 bit in the USART_CR1 register.

When the transmit enable bit (TEN) is set, the data in the transmit shift register is output on

the USART_TX pin and the corresponding clock pulses are output on the USART_CK pin.

Character transmission

During a USART transmission, data shifts out least significant bit first on the USART_TX

pin. In this mode, the USART_DR register consists of a buffer (TDR) between the internal

bus and the transmit shift register (see Figure 81).

Every character is preceded by a start bit which is a logic level low for one bit period. The

character is terminated by a configurable number of STOP bits.

The following STOP bits are supported by USART.

Note:

The TEN bit should not be reset during transmission of data.Resetting the TEN bit during

the transmission will corrupt the data on the USART_TX pin as the baud rate counters will

get frozen.The current data being transmitted will be lost.

An idle frame will be sent after the TEN bit is enabled.

Configurable STOP bits during transmission

The number of STOP bits to be transmitted with every character can be programmed in

Control register 3, bits 5,4.

•

1 STOP bit: This is the default value of number of STOP bits.

•

2 STOP bits: This will be supported by normal mode USART.

An idle frame transmission will include the STOP bits.

A break transmission consists of 10 low bits followed by the configured number of STOP bits

(when m = 0) and 11 low bits followed by the configured number of STOP bits (when m = 1).

It is not possible to transmit long breaks (break of length greater than 10/11 low bits).

Figure 83. Configurable STOP bits

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Start

Bit

Stop

Bit

Start

Bit

8-bit Word length (M bit is reset)

Possible

Parity

Bit

Data Frame

Next Data Frame

****

** LBCL bit controls last data clock pulse

CLOCK

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Start

Bit

2 Stop

Bits

Start

Bit

Possible

Parity

Bit

Data Frame

Next Data Frame

a) 1 Stop Bit

b) 2 Stop Bits

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