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RM0312 датащи(PDF) 180 Page - STMicroelectronics |
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RM0312 датащи(HTML) 180 Page - STMicroelectronics |
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180 / 275 page ![]() Inter-integrated circuit (I2C) interface RM0312 180/275 DocID022352 Rev 3 Master receiver Following the address transmission and after clearing ADDR, the I2C interface enters Master Receiver mode. In this mode the interface receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: • An acknowledge pulse if the ACK bit is set • The RXNE bit is set and an interrupt is generated if the ITEVTEN and ITBUFEN bits are set (Figure 69 & Figure 70). If the RXNE bit is set and the data in the DR register was not read before the end of the next data reception, the BTF bit is set by hardware and the interface waits for the BTF bit to be cleared by reading I2C_SR1 and then I2C_DR, stretching SCL low. Figure 70. Transfer sequence diagram for master receiver 1. Legend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge, EVx= Event (with interrupt if ITEVTEN=1) EV5: SB=1, cleared by reading SR1 register followed by writing DR register. EV6: ADDR=1, cleared by reading SR1 register followed by reading SR3. In 10-bit master receiver mode, this sequence should be followed by writing CR2 with START = 1. EV6_1: no associated flag event, used for 1 byte reception only. Program ACK=0 and STOP=1 after clearing ADDR. EV7: RXNE=1, cleared by reading DR register. EV7_1: RXNE=1, cleared by reading DR register, program ACK=0 and STOP request EV9: ADD10=1, cleared by reading SR1 register followed by writing DR register. 2. If a single byte is received, it is NA. 3. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence. 4. The EV7 event stretches SCL low if the software sequence is not completed before the end of the next byte reception. 5. The EV7_1 software sequence must be completed before the ACK pulse of the current byte transfer. 7-bit master receiver 10-bit master receiver S Address A Data1 A(1) Data2 A ..... DataN NA P EV5 EV6 EV7 EV7 EV7_1 EV7 S Header A Address A EV5 EV9 EV6 S r Header A Data1 A(1) ..... EV5 EV6 EV7 Data2 A EV7 DataN NA P EV7_1 EV7 ai17540c |
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