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RM0312 датащи(PDF) 184 Page - STMicroelectronics |
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RM0312 датащи(HTML) 184 Page - STMicroelectronics |
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184 / 275 page ![]() Inter-integrated circuit (I2C) interface RM0312 184/275 DocID022352 Rev 3 19.5 I2C low power modes 19.6 I2C interrupts Table 38. I2C interface behavior in low power modes Mode Description Wait No effect on I2C interface. I2C interrupts cause the device to exit from Wait mode. Halt In slave mode: Communication is reset, except for configuration registers. Device is in slave mode. Wakeup from Halt interrupt is generated if ITEVTEN = 1 and address matched (including allowed headers). The matched address is not acknowledged in Halt mode so the master has to send it again when the CPU is woken up to receive an acknowledge. If NOSTRETCH = 0, SCLH will be stretched after acknowledge pulse in Halt mode until WUFH is cleared by software; None of the flags are set by the address which wakes up the CPU. In master mode: Communication is frozen until the CPU is woken up. Wakeup from Halt flag and interrupt are generated if ITEVTEN=1 and there is a HALT instruction. Note: It is forbidden to enter Halt mode while a communication is on going. Table 39. I2C Interrupt requests Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt Start bit sent (Master) SB ITEVTEN Yes No Address sent (Master) or Address matched (Slave) ADDR 10-bit header sent (Master) ADD10 Stop received (Slave) STOPF Data byte transfer finished BTF Wakeup from Halt WUFH ITEVTEN Yes Receive buffer not empty RXNE ITEVTEN and ITBUFEN No Transmit buffer empty TXE Bus error BERR ITERREN Arbitration loss (Master) ARLO Acknowledge failure AF Overrun/underrun OVR |
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