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RM0312 датащи(PDF) 177 Page - STMicroelectronics

номер детали RM0312
подробное описание детали  STM8TL5xxx microcontroller family
PDF  275 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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RM0312 датащи(HTML) 177 Page - STMicroelectronics

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RM0312
Inter-integrated circuit (I2C) interface
200
The peripheral input clock frequency must be at least:
1 MHz in Standard mode
4 MHz in Fast mode
SCL master clock generation
The CCR bits are used to generate the high and low level of the SCL clock, starting from the
generation of the rising and falling edge (respectively). As a slave may stretch the SCL line,
the peripheral checks the SCL input from the bus at the end of the time programmed in
TRISE bits after the rising edge generation.
If the SCL line is low, it means that a slave is stretching the bus, and the high level
counter stops until the SCL line is detected high. This allows to guarantee the minimum
HIGH period of the SCL clock parameter.
If the SCL line is high, the high level counter keeps on counting.
Indeed, the feedback loop from the SCL rising edge generation by the peripheral to the SCL
rising edge detection by the peripheral takes time even if no slave stretches the clock. This
loopback duration is linked to SCL rising time (impacting SCL VIH input detection), plus
delay due to the analog noise filter present on SCL input path, plus delay due to internal
SCL input synchronization with I2C Peripheral clock. The maximum time used by the
feedback loop is programmed in TRISE bits, so that the SCL frequency remains stable
whatever the SCL rising time.
Start condition
Setting the START bit causes the interface to generate a Start condition and to switch to
Master mode (MSL bit set) when the BUSY bit is cleared.
Note:
In master mode, setting the START bit causes the interface to generate a Re-Start condition
at the end of the current byte transfer.
Once the Start condition is sent:
The SB bit is set by hardware and an interrupt is generated if the ITEVTEN bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address (Figure 69 & Figure 70).



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