LTC1412_15 datasheet(7/16 Pages) LINER

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LTC1412

FUNCTIONAL BLOCK DIAGRA

12-BIT CAPACITIVE DAC

COMP

REF AMP

2.5V REF

REFCOMP

(4.06V)

CSAMPLE

•

D11

BUSY

CONTROL LOGIC

INTERNAL

CLOCK

CONVST

ZEROING SWITCHES

OVDD

OGND

AVDD

DVDD

AIN

–

VREF

AGND

DGND

1412 BD

–

SUCCESSIVE APPROXIMATION

OUTPUT

LATCHES

TEST CIRCUITS

DBN

A) HI-Z TO VOH AND VOL TO VOH

DBN

B) HI-Z TO VOL AND VOH TO VOL

1412 TC01

100pF

DBN

A) VOH TO HI-Z

100pF

DBN

B) VOL TO HI-Z

1412 TC02

Load Circuits for Access Timing

Load Circuits for Output Float Delay

APPLICATIONS INFORMATION

Conversion Details

The LTC1412 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an

analog signal to a 12-bit parallel output. The ADC is

complete with a precision reference and an internal clock.

The control logic provides easy interface to microproces-

sors and DSPs. (Please refer to the Digital Interface

section for the data format.)

Conversion start is controlled by the CS and CONVST

inputs. At the start of the conversion the successive

approximation register (SAR) is reset. Once a conversion

cycle has begun it cannot be restarted.

During the conversion, the internal differential 12-bit

capacitive DAC output is sequenced by the SAR from the

most significant bit (MSB) to the least significant bit

(LSB). Referring to Figure 1, the AIN+ and AIN– inputs are

connected to the sample-and-hold capacitors (CSAMPLE)

during the acquire phase and the comparator offset is

nulled by the zeroing switches. In this acquire phase, a

minimum delay of 50ns will provide enough time for the

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