AN2834 datasheet(25/45 Pages) STMICROELECTRONICS

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AN2834

How to get the best ADC accuracy

3.2.6

Analog source resistance calculation

Let us assume that the maximum error allowed is equal to 1/2 LSB. We will calculate the

maximum source resistance allowed.

Vc is the voltage across the internal CADC capacitor (refer to Figure 15).

Then we have:

Figure 25. Worst case error: VAIN = VREF+

Let ts be the sampling time.

ts = TS/fADC, where Ts is the sampling time evaluated by cycles

(1)

For a given ts, the error corresponding to VAIN = VREF+ is greater than the error

corresponding to VAIN < VREF+ because the CADC capacitor takes more time to charge from

0 V to VAIN when VAIN = VREF+ than it takes when VAIN < VREF+ (refer to Figure 25). So VAIN

= VREF+ is the worst case to be taken into account in the demonstration of the maximum

source resistance.



, where:





Rmax = (RAIN + RADC)max

(2)



N is the ADC resolution (in our case N = 12)



This gives:

. Thus:

(3)



By combining equations (1), (2) and (3), we obtain final formula:

Error

VAIN Vc

–

---

LSB

VAIN = VREF+

VAIN < VREF+

Error(VAIN = VREF+) > Error(VAIN < VREF+)

0 V

Error(VAIN < VREF+)

ai15602

Error(VAIN = VREF+)

Error

VREF+ VREF+ 1e

RmaxCADC

--------------------------------

–







–

---

VREF+

-------------------



RmaxCADC

--------------------------------

–

-----------

Rmax

CADC





------------------------------------------

RAINmax

fADC CADC





-------------------------------------------------------------------

RADCmax

–

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