AN2646 datasheet(12/43 Pages) STMICROELECTRONICS

12 / 43 page

ISO 7816-3 – electronic signal and transmission protocol

AN2646 - Application note

12/43

4.2

Data transfer

Data transfer between the reader and the card occurs through the concerted action of two of

the contact lines: CLK and I/O. The I/O line conveys a single bit of information per unit of

time as defined by the CLK depending on its voltage relative to GND. A 1 bit can be

conveyed either through a +5 V value or through a 0 V value. The actual convention used is

determined by the card and is conveyed to the reader through the "initial character" of the

ATR, which is referenced as TS. To transfer 1 byte of information, 10 bits are actually moved

across the I/O line; the first is always a "start bit" and the last is always a parity bit used to

convey even parity. Considering that the I/O line can be (in one bit period) either in a high

(H) state or a low (L) state, the TS character of the form HLHHLLLLLLH signals that the card

wants to use the "inverse convention," meaning that H corresponds to a 0 and L

corresponds to a 1. A TS character of the form HLHHLHHHLLH signals that the card wants

to use the "direct convention," meaning that H corresponds to a 1 and L corresponds to a 0.

The direct convention and the inverse convention also control the bit ordering with each byte

transferred between the card and the reader. In the direct convention, the first bit following

the start bit is the low-order bit of the byte. Successively higher-order bits follow in

sequence. In the inverse convention, the first bit following the start bit is the high-order bit of

the byte. Successively lower-order bits follow in sequence. Parity for each byte transferred

should be even; this means that the total number of 1 bits in the byte, including the parity bit,

must be an even number.

The I/O line comprises a half-duplex channel; that is, either the card or the reader can

transmit data over the same channel, but they both cannot be transmitting at the same time.

So as part of the power-up sequence, both the reader and the card enter a receive state in

which they are listening to the I/O line. With the start of the reset operation, the reader

remains in the receive state while the card must enter a send state in order to send the ATR

back to the reader. From this point on, the two ends of the channel alternate between send

states and receive states. With a half-duplex channel, there is no reliable way for either end

to asynchronously change a state from send to receive or from receive to send. Rather, if

this is desired, that end must go into a receive state and allow a timeout of the operation in

progress; then a reader end will always try to re-establish a known sequence by re-entering

a send state. The CLK and I/O lines can support a wide variety of data transmission speeds.

The specific speed is defined by the card and is conveyed back to the reader through an

optional character in the ATR. The transmission speed is set through the establishment of

one bit time on the I/O line, which means that an interval is established at which the I/O line

may be sampled in order to read a bit and then each successive bit. This time is defined as

an elementary time unit (ETU) and is established through a linear relationship between

several factors. Note that the TS character is returned before any definition of the ETU can

be made. This is possible because the ETU during the ATR sequence is always specified to

be ETU0=372/(CLK frequency) where the CLK frequency is always between 1 MHz and 5

MHz; in fact, the frequency is almost always selected such that the initial data transfer rate is

9,600 bits per second.

This initial etu is used during answer to reset and is replaced by the work etu during

subsequent transmission. F is the clock rate conversion factor and D is the bit rate

adjustment factor used to determine the work etu in subsequent transmissions.

For internal clock cards:

initial etu = 1/9600 s

work etu = (1/D)*(1/9600) s

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