AN2645 datasheet(30/36 Pages) STMICROELECTRONICS

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Block-by-block compatibility analysis

AN2645

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3.6

Clock controller

The clock controller is broadly compatible across the whole STM8S family range. There are

some small differences which concern the maximum frequency of the high speed external

clock (HSE clock) and the calibration and trimming of the high speed internal clock

frequency (HSI clock).

3.6.1

HSE clock frequency

Depending on the STM8S family, there is a difference in the maximum speed of the HSE

external oscillator clock.

●

In STM8S Performance line, the HSE clock can be used at up to 24 MHz.

●

In STM8S Access line, the HSE clock is limited to 16 MHz.

If the core runs at a frequency higher than 16 MHz one wait state must be inserted for

reading the Flash/EEPROM memory. This is configured by an option byte setting.

The stabilization delay for the HSE oscillator can be configured by the Option byte setting.

The Performance line family supports double the delay duration of the Access line family.

3.6.2

HSI clock frequency

In all STM8S sub-families, the HSI internal oscillator is factory calibrated in intervals of

+/-2% of the range 5/25°C. This value can be trimmed by the user within an interval of

+3/-4% of the range in eight steps using 3 trimming register bits. This permits calibration in

steps of about 1% of the range.

In addition, in access line products only, it is optionally possible to trim the HSI in the same

interval but in 16 steps using 4 calibration bits. This allows you to trim the frequency more

finely, in steps of about 0.5% of the range.

3.7

Memory

3.7.1

Flash program memory

The Flash program memory organization differs slightly in each sub-family. There are three

different Flash densities:

●

High density in the STM8S208x and STM8S207x sub-families

●

Medium density in the STM8S105x subfamily

●

Low density in the STM8S103x and STM8S903x sub-families

The memory is organized in pages:

●

High density and medium density Flash memory are organized in up to 256 pages of

512 bytes each. Each page is divided into 4 blocks of 128 bytes each. A block is the

maximum amount of memory that can be programmed in a single programming cycle.

●

Low density Flash memory is organized in up to 128 pages of 64 bytes. A page

consists of a single block of 64 bytes.

The page size defines the granularity of the User Boot Code area. Refer to the STM8S

datasheets for more details.

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