AN2556 datasheet(28/35 Pages) STMICROELECTRONICS

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New registers

AN2556

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4.3

Emulation dedicated registers

A set of additional four registers are implemented for emulation purpose only. Similar to

XPEREMU, they are write only registers:

XEMU0 (00’EB76h)

XEMU1 (00’EB78h)

XEMU2 (00’EB7Ah)

XEMU3 (00’EB7Ch)

These registers are used by emulators. They have no user action in ST10F273Z4.

4.3.1

Hardware impacts

None.

4.3.2

Software impacts

None. In ST10F269Zx, the address range 00’E800h to 00’EBFFh is mapped to external

memory but is recommended to reserve this space for upward compatibility.

4.4

XMISC register

This register has been created to handle some additional functionalities. To have access to

this register, XMISCEN bit, bit 10 of XPERCON, must be set.

ST10F273Z4: XMISC (EB46h)

XREG

Reset value: 0000h

3210

Reserved

VREG

OFF

CAN

CK2

CAN

PAR

ADC

MUX

RWRWRW

Table 18.

XMISC register description

Bit No.

Bit name

Function

ADCMUX

Port1L ADC Channels Enable

0: Analog inputs on port P5.y can be converted (default configuration).

1: Analog inputs on Port P1.z can be converted. Only 8 channels can be

managed.

1CANPAR

CAN Parallel Mode Selection

0: CAN2 is mapped on P4.4/P4.7, while CAN1 is mapped on P4.5/P4.6.

1: CAN1 and CAN2 are mapped in parallel on P4.5/P4.6. This is effective

only if both CAN1 and CAN2 are enabled (bits CAN1EN and CAN2EN set in

XPERCON register). If CAN1 is disabled, CAN2 remains on P4.4/P4.7 even

if bit CANPAR is set.

CANCK2

CAN Clock divided by 2 disable

0: Clock provided to CAN modules is CPU clock divided by 2 (mandatory

when fCPU is higher than 40 MHz).

1: Clock provided to CAN modules is the direct CPU clock.

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