AN2284 datasheet(17/40 Pages) STMICROELECTRONICS

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AN2284

7 ISO 7816-3 - Electronic Signal and Transmission Protocol

17/40

character of the form HLHHLHHHLLH signals that the card wants to use the "direct

convention," meaning that H corresponds to a 1 and L corresponds to a 0.

The direct convention and the inverse convention also control the bit ordering with each byte

transferred between the card and the reader. In the direct convention, the first bit following the

start bit is the low-order bit of the byte. Successively higher-order bits follow in sequence. In the

inverse convention, the first bit following the start bit is the high-order bit of the byte.

Successively lower-order bits follow in sequence. Parity for each byte transferred should be

even; this means that the total number of 1 bits in the byte, including the parity bit, must be an

even number.

The I/O line comprises a half-duplex channel; that is, either the card or the reader can transmit

data over the same channel, but they both cannot be transmitting at the same time. So as part

of the power-up sequence, both the reader and the card enter a receive state in which they are

listening to the I/O line. With the commencement of the reset operation, the reader remains in

the receive state while the card must enter a send state in order to send the ATR back to the

reader. From this point on, the two ends of the channel alternate between send states and

receive states. With a half-duplex channel, there is no reliable way for either end to

asynchronously change a state from send to receive or from receive to send. Rather, if this is

desired, that end must go into a receive state and allow a time-out of the operation in progress;

then a reader end will always try to re-establish a known sequence by re-entering a send state.

The CLK and I/O lines can support a wide variety of data transmission speeds. The specific

speed is defined by the card and is conveyed back to the reader through an optional character

in the ATR. The transmission speed is set through the establishment of one bit time on the I/O

line, which means that an interval is established at which the I/O line may be sampled in order

to read a bit and then each successive bit. This time is defined as an elementary time unit (etu)

and is established through a linear relationship between several factors. Note that the TS

character was returned before any definition of the etu could be made. This is possible because

the etu during the ATR sequence is always specified to be etu0=372/(CLK frequency) where

the CLK frequency is always between 1MHz and 5 MHz; in fact, the frequency is almost always

selected such that the initial data transfer rate is 9,600 bits per second.

7.0.3

Answer to Reset: ATR

Once an RST signal is sent from the reader to the card, the card must respond with the first

character of the ATR within 40,000 CLK cycles. The card might not respond with an ATR for a

number of reasons, the most prevalent being that the card is inserted incorrectly into the reader

(probably upside down). In some instances, the card may not be functioning because it has

been damaged or broken. Whatever the case, if the ATR is not returned within the prescribed

time, the reader should begin a sequence to power down the card. During this sequence, the

reader sets the RST, CLK, and I/O lines low and drops voltage on the VCC line to nominal 0

(that is, less than 0.4V).

The ATR is a string of characters returned from the card to the reader following the successful

completion of the power-up sequence. As defined in ISO/IEC 7816-3, the ATR consists of 33 or

fewer characters comprising the following elements:

●

TS - a mandatory initial character

●

T0 - a mandatory format character

●

TAi TBi TCi TDi-optional interface characters

●

T1, T2,TK-optional historical characters

●

TCK - a conditional check character

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