LTC4232

12

4232fb

For more information www.linear.com/LTC4232

APPLICATIONS INFORMATION

Power Good Indication

In addition to setting the foldback current limit threshold,

the FB pin is used to determine a power good condition.

The Figure 1 application uses an external resistive divider

on the OUT pin to drive the FB pin. The PG comparator

indicates logic high when OUT pin rises above 10.5V. If the

OUT pin subsequently falls below 10.3V the comparator

toggles low. On the LTC4232 the PG comparator drives

high when the FB pin rises above 1.235V and low when

it falls below 1.215V.

Once the PG comparator is high the GATE pin voltage is

monitored with respect to the OUT pin. Once the GATE

minus OUT voltage exceeds 4.2V the PG pin goes high.

This indicates to the system that it is safe to load the OUT

pin while the MOSFET is completely turned “on”. The PG

pin goes low when the GATE is commanded off (using

the UV, OV or SENSE pins) or when the PG comparator

drives low.

Design Example

triggers an automatic restart of the power-up sequence.

As mentioned previously the charge-up time is the out-

put voltage (12V) divided by the output rate of 0.3V/ms

resulting in 40ms. The peak power dissipation of 12V at

100mA (or 1.2W) is within the SOA of the pass MOSFET

for 40ms (see MOSFET SOA curve in the Typical Perfor-

mance Characteristics section).

Next the power dissipated in the MOSFET during overcur-

rent must be limited. The active current limit uses a timer

to prevent excessive energy dissipation in the MOSFET.

Theworst-casepowerdissipationoccurswhenthevoltage

versus current profile of the foldback current limit is at

the maximum. This occurs when the current is 6.1A and

the voltage is one half of the 12V or 6V. See the Current

LimitThresholdFoldbackintheTypicalPerformanceChar-

acteristics section to view this profile. In order to survive

36W, the MOSFET SOA dictates a maximum time of 10ms

(see SOA graph). Use the internal 2ms timer invoked by

FLT pin needs to pull-down on the UV pin to restart the

power-up sequence.

The values for overvoltage, undervoltage and power good

thresholds using the resistive dividers on the UV, OV and

FB pins match the requirements of turn-on at 9.88V and

turn-off at 15.2V.

The final schematic in Figure 5 results in very few external

components. The pull-up resistor, R1, connects to the

voltage at a ratio:

Layout Considerations

In Hot Swap applications where load currents can be 5A,

narrowPCBtracksexhibitmoreresistancethanwidertracks

and operate at elevated temperatures. The minimum trace

width for 1oz copper foil is 0.02" per amp to make sure

the trace stays at a reasonable temperature. Using 0.03"

per amp or wider is recommended. Note that 1oz copper

exhibits a sheet resistance of about 0.5mΩ/square. Small

resistances add up quickly in high current applications.

Figure 5. 5A, 12V Card Resident Application

The inrush current is defined by the current required to

charge the output capacitor using the fixed 0.3V/ms GATE

charge-up rate. The inrush current is defined as:

0.3V

ms











 = 330µF •

0.3V

ms











 = 100mA

ADC

226k

C1

1µF

20k

12V

140k

20k

R2

20k

4232 F05

330µF

UV

OUT

FB

PG

GATE

GND

LTC4232

OV

TIMER

FLT

+

12V

5A

R1

10k

20k

150k

Z1

Z1: DIODES INC. SMAJ22A