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HOW TO MINIMIZE THE ST7 POWER CONSUMPTION

external event, or regularly woken-up by an internal timer event. In our case, we decided to put

the ST7 core in Wait For Interrupt state, with one timer active to regularly wake up the core.

This enables the core to refresh the WDG to prevent a watchdog reset. The clock driving the

active peripherals and the core when it is active corresponds to the slowest clock available. It

is the oscillator clock divided by 2 then divided by 16. So the clock driving the peripherals and

the following configuration.

6.3.1 Measurement Configuration

In this mode, the MCU is configured as below, but of course in the application this configura-

tion may differ, in particular the I/O port used.

- The optimum Slow mode is selected with the divided external clock factor equal to 32. This

the Miscellaneous Register (MISCR) the SMS and CP1 & CP0 bits must be set.

- All I/O ports are connected to an external pull-up or pull-down to avoid leakage due to floating

inputs.

- The Watchdog Timer (WDG) is active with a maximum time-out period. The WDG Control

Register (WDGCR) must be loaded with the value FFh and the TB1 & TB0 bits must be set.

- One 16-bit timer is used to wake-up the core at regular intervals. The timer event period must

be adjusted to its maximum value to allow the core to refresh the WDG and to avoid a WDG

bits must be cleared.

- The external clock is selected on the unused 16-bit timer with a continuous level on the ex-

ternal clock pin. In the Control Register (CR2) CC1, CC0 bits must be set.

clock on timer B. The continuous level on the timer input clock is already done internally, as

there is no external I/O connected to the internal Timer B circuit. It stops the counter on timer

B, because if external clock is not available, programming the external clock configuration

stops the counter.

On the contrary, if Timer B is used to wake-up the micro, the user has to select the external

clock on Timer A and to fix a continuous level on the external clock pin. But be aware, on

Timer A there is only one input capture and one output compare instead of two on Timer B.

– The main loop contains a Wait For Interrupt “WFI” instruction.

– Continuous low level on each PWM output (reset state)

– The A/D converter must be switched off. In the A/D Control/Status Register (CSR), the

ADON bit must be cleared.

– The SPI and SCI are unused.