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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AN910 датащи(PDF) 25 Page - STMicroelectronics |
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AN910 датащи(HTML) 25 Page - STMicroelectronics |
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25 / 51 page  25/51 ST7 AND ST9 PERFORMANCE BENCHMARKING 7 MCU CORE ARCHITECTURE ANALYSIS This section presents, for the different MCUs, the main parameters of the core architecture which are significant for benchmark result analysis. 7.1 PARAMETER DESCRIPTION The significant parameters of core architecture are the following ones: On-chip/Off-chip buses - on-chip buses address bus size data/program memory bus sizes register bus size (if any) - off-chip buses (if any) address bus size data/program memory bus size multiplexing Memory Spaces Harvard organization Von Neumann organization - special register space (if any) - data/program memory spaces - interrupt vector table location and size Arithmetic Logic Unit datapath size - standard operations - special functions and performance Instruction processing Standard Prefetch mechanism - queue size - predecoding (if any) - address alignment Cpu internal buses address bus size, data bus size register bus (if any) Instruction set Cisc/Risc encoding - Clock Per Instruction (CPI) - average Clock Per Instruction - Instruction Length (IL) - average Instruction Length - special addressing modes - special instructions Programming model Register file Accumulator(s) Mixed register file/accumulator - list of registers (they may be outside the cpu) - multitasking capabilities MOVE Rd,Rs ADD Rd,#2 + / x LDAA #8, X ADDA #A0 CPU |
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