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RM0352 датащи(PDF) 26 Page - STMicroelectronics |
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RM0352 датащи(HTML) 26 Page - STMicroelectronics |
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26 / 138 page ![]() Clock and reset management unit RM0352 26/138 DocID024647 Rev 1 5.3.5 System reset request The system reset request is generated by the debug circuitry of the Cortex-M0. The debugger writes to the SYSRESETREQ bit of the “Application Interrupt and Reset Control Register” (AIRCR). The system reset request does not affect the debugger thus allowing the debugger to remain connected during the reset sequence. For more details on the Cortex- M0 system control and ID registers, refer to section B3.2.2 of “ARMv6-M Architecture Reference Manual”. 5.3.6 Lockup reset The Cortex-M0 generates an output LOCKUP which indicates that the core is in the architected lock-up state resulting from an unrecoverable exception. The LOCKUP signal is used to generate reset in the Brain device. This reset will affect the Cortex-M0, the Flash controller, and all the peripherals. The LOCKUP signal does not reset the Cortex-M0 debug circuitry. For more information on the LOCKUP state the reader is referred to section B1.5.15 of “ARMv6-M Architecture Reference Manual”. 5.3.7 Recall done The Flash controller must perform the RECALL operation of the Flash memory after power- up, during this time the trimming codes of the Flash memory are restored from the memory array to the Flash registers. During the RECALL time the processor is held in reset when the RECALL_DONE signal is set to one, the processor can leave the reset state and begin program fetch from Flash. |
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