RM0352 datasheet(80/138 Pages) STMICROELECTRONICS

80 / 138 page

I2C bus interface

RM0352

80/138

DocID024647 Rev 1

10.2.5

I2C status register (I2C_SR)

Table 75. I2C status register (I2C_SR)

Address:

I2CBaseAddress + 0x14

Type:

Reset:

0x00000000

I2C status register (I2C_SR)

26 25 24 23 22

19 18 17 16 15 14 13

Description:

The status code word includes the status of the transfer in terms of:

•

Operation type (master-read, master-write, write-to-slave, read-from-

slave)

•

Status (successfully, abort)

•

Cause of the abort occurrence

•

Type (standard frame, general call, hardware general call)

•

Length of the transaction (in terms of byte number).

•

In SMBUS mode:

–

SMBus device default address

–

Packet error checking register

–

Dual addressing flag

On the completion of a master or slave operation, the interrupt bit

I2C_RISR:MTD or I2C_RISR:STD is asserted and the related status of the

operation is stored in the current register.

[29] DUALF: dual flag (slave mode)

0: received address matched with the “Slave Address” (SA7)

1: received address matched with “Dual Slave Address” (DSA7)

•

Cleared by hardware after a STOP condition or repeated START

condition, bus error or when

PE = 0.

[28:21] PECR: packet error checking register

This register contains the actual PEC calculated by hardware CRC-8 when

I2C_CR: ENPEC = 1.

RM0352 датащи(PDF) 80 Page - STMicroelectronics

RM0352 датащи(HTML) 80 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL