RM0352 datasheet(126/138 Pages) STMICROELECTRONICS

126 / 138 page

UART (universal asynchronous receive transmit)

RM0352

126/138

DocID024647 Rev 1

12.6.7

Line control register, UARTLCR_H

The UARTLCR_H register is the line control register. This register accesses bits 29 to 22 of

the UART line control register, UARTLCR.

All the bits are cleared to 0 when reset.

Table 123 lists the register bit assignments.

The UARTLCR_H, UARTIBRD, and UARTFBRD registers form the single 30-bit wide

UARTLCR register that is updated on a single write strobe generated by a UARTLCR_H

write. So, to internally update the contents of UARTIBRD and/or UARTFBRD, a

UARTLCR_H write must always be performed at the end (as indicated in

Note:below).

Table 123. UARTLCR_H register

Bits

Name

Function

15:8

RESERVED, do not modify, read as zero.

SPS

Stick parity select.

0 = stick parity is disabled

1 = either:

– if the EPS bit is 0 then the parity bit is transmitted and checked as 1

– if the EPS bit is 1 then the parity bit is transmitted and checked as 0.

This bit has no effect when the PEN bit disables parity checking and generation. See

Table 124 on

page 127 for the parity truth table.

6:5

WLEN

Word length. These bits indicate the number of data bits transmitted or received in a frame as

follows:

b11 = 8 bits

b10 = 7 bits

b01 = 6 bits

b00 = 5 bits.

FEN

Enable FIFOs:

0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers

1 = transmit and receive FIFO buffers are enabled (FIFO mode).

STP2

Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The

receive logic does not check for two stop bits being received.

EPS

Even parity select. Controls the type of parity the UART uses during transmission and reception:

0 = odd parity. The UART generates or checks for an odd number of 1 s in the data and parity bits.

1 = even parity. The UART generates or checks for an even number of 1 s in the data and parity

bits.

This bit has no effect when the PEN bit disables parity checking and generation. See

Table 124 on

page 127 for the parity truth table.

PEN

Parity enable:

0 = parity is disabled and no parity bit added to the data frame

1 = parity checking and generation is enabled.

See

Table 124 on page 127 for the parity truth table.

BRK

Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after

completing transmission of the current character. For the proper execution of the break command,

the software must set this bit for at least two complete frames.

For normal use, this bit must be cleared to 0.

RM0352 датащи(PDF) 126 Page - STMicroelectronics

RM0352 датащи(HTML) 126 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL