RM0352 datasheet(114/138 Pages) STMICROELECTRONICS

114 / 138 page

SPI (serial peripheral interface)

RM0352

114/138

DocID024647 Rev 1

Provision of the individual outputs in addition to a combined interrupt output, enables the

use of either a global interrupt service routine, or modular device drivers to handle

interrupts.

The transmit and receive dynamic data flow interrupts

SSPTXINTR and SSPRXINTR have

been separated from the status interrupts, so that data can be read or written in response to

only the FIFO trigger levels.

The status of the individual interrupt sources can be read from the SSPRIS and SSPMIS

registers.

11.5.1

SSPRXINTR

The receive interrupt is asserted when there are four or more valid entries in the receive

FIFO.

11.5.2

SSPTXINTR

The transmit interrupt is asserted when there are four or fewer valid entries in the transmit

FIFO. The transmitter interrupt SSPTXINTR is not qualified with the PrimeCell SSP enable

signal, and this enables operation in either of the following ways:

•

Data can be written to the transmit FIFO prior to enabling the PrimeCell SSP and the

interrupts.

•

The PrimeCell SSP and interrupts can be enabled so that data can be written to the

transmit FIFO by an interrupt service routine.

11.5.3

SSPRORINTR

The receive overrun interrupt

SSPORINTR is asserted when the FIFO is already full and an

additional data frame is received, causing an overrun of the FIFO. Data is overwritten in the

receive shift register, but not the FIFO.

11.5.4

SSPRTINTR

The receive timeout interrupt is asserted when the receive FIFO is not empty and the

PrimeCell SSP has remained idle for a fixed 32-bit period. This mechanism ensures that the

user is aware that data is still present in the receive FIFO and requires servicing. This

interrupt is deasserted if the receive FIFO becomes empty by subsequent reads, or if new

data is received on

SSPRXD. It can also be cleared by writing to the RTIC bit in the SSPICR

The interrupts are also combined into a single output SSPINTR, that is, an OR function of

the individual masked sources. This output is connected to the system interrupt controller

(NVIC) to provide another level of masking on an individual per peripheral basis.

The combined PrimeCell SSP interrupt is asserted if any of the four individual interrupts

above are asserted and enabled.

RM0352 датащи(PDF) 114 Page - STMicroelectronics

RM0352 датащи(HTML) 114 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL