AN4406 datasheet(9/27 Pages) STMICROELECTRONICS

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AN4406

Impact of the MOSFET parasitic capacitances

So, for the time TT for voltage VHB to reach Vin, TT can be expressed as:

Equation 4

Note:

In order to guarantee the ZVS transitions, the value of TT must not exceed the dead time TD

to ensure that the switch is turned on with zero VDS voltage.

From the previous equation, it is possible to note that converter operation may be influenced

by the parasitic capacitances of the MOSFET, so MOSFET's switching behavior can be

affected by the parasitic capacitances between the three terminals of the device: gate-to-

source (CGS), gate-to-drain (CGD) and drain-to-source (CDS) capacitances.

These capacitance values are non-linear and a function of device structure, geometry, and

bias voltages VDS. The magnitudes are largely determined by the size of the chip and cell

topology used. Manufacturers do not generally specify CGD, CGS and CDS directly, but the

magnitudes and the profile of the parasitic capacitances are given in datasheets by the

voltage VDS and also by the technology of the MOSFET.

In Figure 5, the Coss parasitic capacitances of two MOSFETs with the same die size but with

different technologies are shown.

Figure 5. Output capacitances of two devices with same die size but different

technologies

The technology with the larger density cell (MDmesh™ M5) clearly has a higher COSS

parasitic capacitance value at low VDS voltages. This aspect is not only due to the cellular

density, but also the different doping process used to obtain the same VDSS. In fact, the two

analyzed devices have same die size, same BVDSS, but different RDS(on) owing to the

different technologies adopted.

The theory introduced earlier helps explain the impact of MOSFET parasitic capacitances

when it used on resonant topologies.

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